Showing papers in "IEEE Transactions on Electron Devices in 2011"

An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation

Abstract: The multilevel capability of metal oxide resistive switching memory was explored for the potential use as a single-element electronic synapse device. TiN/HfOx/AlOx/ Pt resistive switching cells were fabricated. Multilevel resistance states were obtained by varying the programming voltage amplitudes during the pulse cycling. The cell conductance could be continuously increased or decreased from cycle to cycle, and about 105 endurance cycles were obtained. Nominal energy consumption per operation is in the subpicojoule range with a maximum measured value of 6 pJ. This low energy consumption is attractive for the large-scale hardware implementation of neuromorphic computing and brain simulation. The property of gradual resistance change by pulse amplitudes was exploited to demonstrate the spike-timing-dependent plasticity learning rule, suggesting that metal oxide memory can potentially be used as an electronic synapse device for the emerging neuromorphic computation system.

Performance Limits of Monolayer Transition Metal Dichalcogenide Transistors

Abstract: The performance limits of monolayer transition metal dichalcogenide ( MX2) transistors are examined with a ballistic MOSFET model. Using an ab initio theory, we calculate the band structures of 2-D transition MX2. We find the lattice structures of monolayer MX2 remain the same as the bulk MX2. Within the ballistic regime, the performances of monolayer MX2 transistors are better compared with those of the silicon transistors if a thin high-κ gate insulator is used. This makes monolayer MX2 promising 2-D materials for future nanoelectronic device applications.

Modeling the Universal Set/Reset Characteristics of Bipolar RRAM by Field- and Temperature-Driven Filament Growth

Abstract: Resistive switching memory (RRAM) devices generally rely on the formation/dissolution of conductive filaments through insulating materials, such as metal oxides and chalcogenide glasses. Understanding the mechanisms for filament formation and disruption in resistive switching materials is a critical step toward the development of reliable and controllable RRAM for future-generation storage. In particular, the capability to control the filament resistance and the reset current through the compliance current during filament formation may provide a key signature to clarify the switching mechanism. This paper provides a physically based explanation for the universal resistance switching in bipolar RRAM devices. A numerical model of filament growth based on thermally activated ion migration accounts for the resistance switching characteristics. The same physical picture is extended to numerically model the reset transition. The impact of migration parameters and experimental setup on the set/reset characteristics is discussed through numerical simulations.

The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps

Abstract: One of the most important degradation modes in CMOS technologies, the bias temperature instability (BTI) has been known since the 1960s. Already in early interpretations, charge trapping in the oxide was considered an important aspect of the degradation. In their 1977 paper, Jeppson and Svensson suggested a hydrogen-diffusion controlled mechanism for the creation of interface states. Their reaction-diffusion model subsequently became the dominant explanation of the phenomenon. While Jeppson and Svensson gave a preliminary study of the recovery of the degradation, this issue received only limited attention for many years. In the last decade, however, a large number of detailed recovery studies have been published, showing clearly that the reaction-diffusion mechanism is inconsistent with the data. As a consequence, the research focus shifted back toward charge trapping. Currently available advanced charge-trapping theories based on switching oxide traps are now able to explain the bulk of the experimental data. We give a review of our perspective on some selected developments in this area.

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

Abstract: In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

A Versatile Memristor Model With Nonlinear Dopant Kinetics

Abstract: The need for reliable models that take into account the nonlinear kinetics of dopants is nowadays of paramount importance, particularly with the physical dimensions of electron devices shrinking to the deep nanoscale range and the development of emerging nanoionic systems such as the memristor. In this paper, we present a novel nonlinear dopant drift model that resolves the boundary issues existing in previously reported models that can be easily adjusted to match the dynamics of distinct memristive elements. With the aid of this model, we examine switching mechanisms, current-voltage characteristics, and the collective ion transport in two terminal memristive devices, providing new insights on memristive behavior.

A Current-Transient Methodology for Trap Analysis for GaN High Electron Mobility Transistors

Abstract: Trapping is one of the most deleterious effects that limit performance and reliability in GaN HEMTs. In this paper, we present a methodology to study trapping characteristics in GaN HEMTs that is based on current-transient measurements. Its uniqueness is that it is amenable to integration with electrical stress experiments in long-term reliability studies. We present the details of the measurement and analysis procedures. With this method, we have investigated the trapping and detrapping dynamics of GaN HEMTs. In particular, we examined layer location, energy level, and trapping/detrapping time constants of dominant traps. We have identified several traps inside the AlGaN barrier layer or at the surface close to the gate edge and in the GaN buffer.

Process Technology Variation

Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Junctionless Multiple-Gate Transistors for Analog Applications

Abstract: This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM)

Abstract: A physics-based compact device model is developed for the conducting-bridge random-access memory (CBRAM). By considering the dependence of ion migration velocity on the electric field, the vertical and lateral growth/dissolution dynamics for the metallic filament are investigated. Both time-dependent transient and “quasi-static” switching characteristics of the CBRAM are captured. Moreover, the I-V characteristics of the CBRAM can be reproduced. By further considering the compliance effect on the size of the metallic filament, the on-state resistance modulation is fitted, and the multilevel capability is included in the model. This model is verified by the experiments data from the Ag/Ge0.3Se0.7-based CBRAM cells. This model reveals that experimentally measured switching parameters such as the threshold voltage and the cell resistance are dynamic quantities that depend on the programming duration time. The time-dependent switching process of the CBRAM is quantified, thus paving the way for a compact SPICE model for circuit simulation.

Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors

Abstract: We derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge-potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 1019 cm-3 for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

Abstract: Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling.

Theory of the Junctionless Nanowire FET

Abstract: In this paper, we model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction-based FET. The analytical model worked out here assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior. Most notably, it aims to clarify the motivation for its nearly ideal subthreshold slope and its excellent on-state current while being a depletion device with lower electron mobility due to impurity scattering. At the same time, the model clarifies a constraint binding the allowable value of the doping density per unit length and its impact on the overall device performance. The device variability and the parasitic source/drain resistances are identified as the most important limitations of the JL nanowire field-effect transistor.

A Physical Model of the Temperature Dependence of the Current Through $\hbox{SiO}_{2}\hbox{/}\hbox{HfO}_{2}$ Stacks

Abstract: In this paper, we investigate the characteristics of the defects responsible for the leakage current in the SiO2 and SiO2/HfO2 gate dielectric stacks in a wide temperature range (6 K-400 K). We simulated the temperature dependence of the I -V characteristics both at positive and negative gate voltages by applying the multiphonon trap-assisted tunneling model describing the charge transport through the dielectric. In the depletion/weak inversion regime, the current is limited by the supply of carriers available for tunneling. In strong inversion, the temperature dependence is governed by the charge transport mechanisms through the stacks; in particular, in SiO2/HfO2 dielectric stacks, the coupling of the injected carriers with the dielectric phonons at the trap sites is the dominant mechanism. Matching the simulation results to the measurement data allows extracting important trap parameters, e.g., the trap relaxation and ionization energies, which identify the atomic structure of the electrically active defects in the gate dielectric.

Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory

Abstract: In this paper, a 3-D NAND Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on NAND Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line NAND Flash memory application.

Electrical and Photosensitive Characteristics of a-IGZO TFTs Related to Oxygen Vacancy

Abstract: The electrical and photosensitive characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) related to the oxygen vacancies VO are discussed. With the filling of VO of ratio from 14 to 8, the electron density of the a-IGZO channel decreases from 7.5 to 3.8 ( ×1016 cm-3); the saturation mobility of the TFT decreases from 3.1 to 1.4 cm-2/(V · s); the threshold voltage increases from 7 to 11 V for the TFT with a lower on-current; and the subthreshold slope increases from 2.4 to 4.4 V/dec for the TFT with a higher interface defect density of 4.9 × 1011 cm-2, the worst electrical stability of Vth ~ 10 V, and a hysteresis-voltage decrease from 3.5 to 2 V. The photoreaction properties of a-IGZO TFTs are also sensitive to the oxygen-content-related absorption of the a-IGZO channel. With the lowest content of oxygen in the channel, the TFT has the largest photocurrent gain of 50 μA (Vg = 30 V; Vd = 10 V) and decrease in Vth ( Vth V) at a high light intensity. The light-induced change of TFT characteristics is totally reversible with the time constant for recovery of about 2.5 h.

Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics

Abstract: Thin-film transistors (TFTs) are a key element of flexible electronics implemented on low-cost substrates. Most TFT technologies, however, have only monotype-either n- or p-type-devices. In this paper, we propose a novel design style Pseudo-CMOS for flexible electronics that uses only monotype single-VT TFTs but has comparable performance with the complementary-type or dual-VT designs. The manufacturing cost and complexity can therefore be significantly reduced, whereas the circuit yield and reliability are enhanced with built-in postfabrication tunability. Digital cells are fabricated in two different TFT technologies, i.e., p-type self-assembled-monolayer-organic TFTs and n-type metal-oxide InGaZnO TFTs, to validate the proposed Pseudo-CMOS design style. To the best of our knowledge, this is the first design solution that has been experimentally proven to achieve superior performance for both types of TFT technologies.

Impact of Temperature on the Resistive Switching Behavior of Embedded $\hbox{HfO}_{2}$ -Based RRAM Devices

Abstract: Back-end-of-line integrated 1 × μm2 TiN/HfO2/Ti/TiN MIM memory devices in a 0.25- μm complementary metal-oxide-semiconductor technology were built to investigate the conduction mechanism and the resistive switching behavior as a function of temperature. The temperature-dependent I- V characteristics in fresh devices are attributed to the Poole-Frenkel mechanism with an extracted trap energy level at φ ≈ 0.2 eV below the HfO2 conduction band. The trap level is associated with positively charged oxygen vacancies. The electroformed memory cells show a stable bipolar switching behavior in the temperature range from 213-413 K. The off -state current increases with temperature, whereas the on-state current can be described by a weak metallic behavior. Furthermore, the results suggest that the I-V cycling not only induces significant changes in the electrical properties of the MIM memory devices, i.e., the increase in the off-state current, but also stronger temperature dependence. The temperature effect on the on-state and off-state characteristics is modeled within the framework of the quantum point-contact model for dielectric breakdown using an effective temperature-dependent confinement potential.

Multi- $V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Abstract: This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT ). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.

RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs

Abstract: This paper presents a radio-frequency (RF) model and extracted model parameters for junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a 3-D device simulator. JLSNW MOSFETs are evaluated for various RF parameters such as cutoff frequency fT, gate input capacitance, distributed channel resistances, transport time delay, and capacitance by the drain-induced barrier lowering effect. Direct comparisons of high-frequency performances and extracted parameters are made with conventional silicon nanowire MOSFETs. A non-quasi-static RF model has been used, along with SPICE to simulate JLSNW MOSFETs with RF parameters extracted from 3-D-simulated Y-parameters. The results show excellent agreements with the 3-D-simulated results up to the high frequency of fT.

Fabrication of a Fractional Order Capacitor With Desired Specifications: A Study on Process Identification and Characterization

Abstract: This paper reports the fabrication of a fractional order element (FOE) with predefined specifications. The FOE is a circuit element similar to resistance, capacitance, and inductance generally used in electrical network. The specifications of integer order elements, i.e., inductance, resistance, and capacitance, are defined by the magnitude only as their exponents are of fixed value, namely, - 1, 0, and +1, respectively. The specialty of FOE is that both its magnitude and exponent value have to be defined, where the value of the exponent dictates the behavior. This paper elaborately discusses the methodology of realizing a fractional order capacitor named here as FOE (or, in general, FOE). It has been found that a FOE can be realized by dipping a capacitive-type probe, coated with a porous film of polymer of particular thickness, into a polarizable medium. The thickness, uniformity, and stability of the porous film, on the electrode, are responsible for different exponent values.

The Effects of Mechanical Bending and Illumination on the Performance of Flexible IGZO TFTs

Abstract: Amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconducting material for use in flexible thin-film-transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. To use these TFTs in flexible applications, their behavior under applied mechanical strain and changing illumination, as well as the influence of bending on reflattened TFTs, needs to be understood. We have fabricated a-IGZO TFTs on flexible substrates and measured their behavior under tensile and compressive strains down to bending radii <; 10 mm. Bending tests were applied in the dark, as well as under 90-lx illumination. Without illumination, the tensile and compressive strains caused a little change in the TFT performance, but the influence of the tensile strain combined with illumination causes changes in the TFT mobility of 15% and changes in threshold voltage of - 0.11 V. By comparison, the performance of illuminated TFTs under the applied compressive strain changes little compared with measurements in the dark. The impact of repeated tensile bending and reflattening shows a similar picture; bending tests carried out in the dark resulted in a nearly constant threshold voltage, but with illumination, we observed a shift of -0.1 V after 40 min of repeated bending.

Operation of a Continuously Frequency-Tunable Second-Harmonic CW 330-GHz Gyrotron for Dynamic Nuclear Polarization

Abstract: The design and the operation of a frequency-tunable continuous-wave (CW) 330-GHz gyrotron oscillator operating at the second harmonic of the electron cyclotron frequency are reported. The gyrotron has generated 18 W of power from a 10.1-kV 190-mA electron beam working in a TE-4,3 cylindrical mode, corresponding to an efficiency of 0.9%. The measured start oscillation current over a range of magnetic field values is in good agreement with theoretical start currents obtained from linear theory for successive high-order axial modes TE-4,3,q, where q = 1-6. Moreover, the observed frequency range in the start current measurement is in reasonable agreement with the frequency range obtained from numerical simulations. The minimum start current was measured to be 33 mA. A continuous tuning range of 1.2 GHz was experimentally observed via a combination of magnetic, voltage, and thermal tuning. The gyrotron output power and frequency stabilities were assessed to be ±0.4% and ±3 ppm, respectively, during a 110-h uninterrupted CW run. Evaluation of the gyrotron output microwave beam pattern using a pyroelectric camera indicated a Gaussian-like mode content of 92% with an ellipticity of 28%. The gyrotron will be used for 500-MHz nuclear magnetic resonance experiments with sensitivity enhanced by dynamic nuclear polarization.

A Physics-Based Analytical Model for 2DEG Charge Density in AlGaN/GaN HEMT Devices

Abstract: In this brief, we present a physics-based analytical model for 2-D electron gas density ns in AlGaN/GaN high-electron mobility transistors. The proposed model accounts for the interdependence between Fermi level Ef and ns. The model is developed by considering the variation of Ef, the first subband E0, the second subband E1, and ns with applied gate voltage Vg. The proposed model is in very good agreement with numerical calculations.

Scaleable Single-Photon Avalanche Diode Structures in Nanometer CMOS Technology

Abstract: Single-photon avalanche photodiodes (SPADs) operating in Geiger mode offer exceptional time resolution and optical sensitivity. Implementation in modern nanometer-scale complementary metal-oxide-semiconductor (CMOS) technologies to create dense high-resolution arrays requires a device structure that is scaleable down to a few micrometers. A family of three SPAD structures with sub-100-Hz mean dark count rate (DCR) is proposed in 130-nm CMOS image sensor technology. Based on a novel retrograde buried n-well guard ring, these detectors are shown to readily scale from 32 to 2 μm with improving DCR, jitter, and yield. One of these detectors is compatible with standard triple-well digital CMOS, and the others bring the first low-DCR realizations at the 130-nm node of shallow-trench-isolation-bounded and enhancement SPADs.

Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs

Abstract: The effects of random dopant fluctuations (RDFs) on the performance of Germanium-source tunnel field-effect transistors (TFETs) is studied using 3-D device simulation. The RDF in the source region is found to have the most impact on threshold voltage variation (σVTH) if the source is moderately doped (1019 cm-3) such that vertical tunneling within the source is dominant. If the source is heavily doped (1020 cm-3) such that lateral tunneling from the source to the channel is dominant, the impact of RDF in the channel region is also significant. RDF-induced threshold voltage variation (σVTH) for an optimally designed Ge-source TFET is relatively modest (σVTH <; 20 mV at Lg = 30 nm), compared with a MOSFET of similar gate length. Supply voltage scaling is not beneficial for reducing TFET σVTH.

A Full-Range Drain Current Model for Double-Gate Junctionless Transistors

Abstract: A drain current model available for full-range operation is derived for long-channel double-gate junctionless transistors. Including dopant and mobile carrier charges, a continuous 1-D charge model is derived by extending the concept of parabolic potential approximation for the subthreshold and the linear regions. Based on the continuous charge model, the Pao-Sah integral is analytically carried out to obtain a continuous drain current model. The proposed model is appropriate for compact modeling, because it continuously captures the phenomenon of the bulk conduction mechanism in all regions of device operation, including the subthreshold, linear, and saturation regions. It is shown that the model is in complete agreement with the numerical simulations for crucial device parameters and all operational voltage ranges.

A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance

Abstract: We propose a modified structure of tunnel field-effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET). STBFET has a large tunneling cross-sectional area with a tunneling distance of ~2 nm. An orientation-dependent nonlocal band-to-band tunneling (BTBT) model was employed to investigate the device characteristics. The feasibility of the STBFET realization using a complementary metal-oxide-semiconductor-compatible process flow has been shown using advanced process calibration with Monte Carlo implantation. STBFET gives a high ION, exceeding 1 mA/μm at IOFF of 0.1 pA/μm with a subthreshold swing below 40 mV/dec. The device also shows better static and dynamic performances for sub-1-V operations. STBFET shows a very good drain current saturation, which is investigated using an ab initio physics-based BTBT model. Furthermore, the simulated ION improvement is validated through analytical calculations. We have also investigated the physical root cause of the large voltage overshoot of TFET inverters. The previously reported impact of Miller capacitance is shown to be of lower importance; the space-charge buildup and its relaxation at the channel drain junction are shown to be the dominant effect of large voltage overshoot of TFETs. The STBFET are shown to have negligible voltage overshoots compared with conventional TFETs.

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

Abstract: A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.

Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study

Abstract: This paper presents a comprehensive full-scale three-dimensional simulation scaling study of the statistical threshold-voltage variability in bulk high-k/metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granularity (MGG) and corresponding workfunction-induced threshold-voltage variability have become important sources of statistical variability in bulk HKMG MOSFETs. It is found that the number of metal grains covering the gate plays an important role in determining the shape of the threshold-voltage distribution and the magnitude of the threshold-voltage variability in scaled devices in the presence of dominant variability sources (MGG, random discrete dopants, and line edge roughness). The placement of metal grains is found to also contribute to the total MGG variability. This paper presents the relative importance of MGG compared with other statistical variability sources. It is found that MGG can distort and even dominate the threshold-voltage statistical distribution when the metal grain size cannot be adequately controlled.