A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Low density parity check decoder for regular LDPC codes

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Method and apparatus for evaluating and optimizing a signaling system

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

High-speed signaling systems with adaptable pre-emphasis and equalization

A resist composition used in a method of forming a resist pattern including applying a resist composition comprising a base component that exhibits increased solubility in an alkali developing solution and a photo-base generator component to a substrate to form a resist film; subjecting the resist film to exposure; baking after subjecting the resist film to exposure, wherein at an exposed portion of the resist film, the base generated from the photo-base generator component upon exposure and an acid provided to the resist film in advance are neutralized, and at an unexposed portion of the resist film, the solubility of the base component in an alkali developing solution is increased by the action of acid provided to the resist film in advance; and subjecting the resist film to alkali development, thereby forming a negative-tone resist pattern.

Resist composition and method of forming resist pattern

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase

Phase interpolator device and method

A noise reduction circuit for reducing the effects of low frequency noise such as wind noise in communications applications is described. In one embodiment, the noise reduction circuit features a high pass filter formed by exploiting the existing off-chip AC coupling capacitances in making the connection to the source of audio signals. The filter may be adaptive to environmental low frequency noise level through programming the shunt resistances. A low-noise wide dynamic range programmable gain amplifier is also described. Adaptive equalization of the audio signal is also described through the utilization of programmable front-end resistors and a back-end audio equalizer.

Low frequency noise reduction circuit architecture for communications applications

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

High-speed serial data transceiver and related methods

High efficiency Class-D speaker drivers have become ubiquitous in battery driven mobile audio applications. Analog switching errors and timing jitter are known limitations to the dynamic range in these types of switching audio drivers. To overcome these limitations the Class-D architecture chosen in this paper provides a low 667 kHz pulse rate. This architecture is based on a 4th-order digital modulator with pulse-width modulation (PWM) feedback. The modulator loop processes the PWM signals at a high 24 MHz clock rate, and provides pulse edge timing resolution within a single clock period of the high-rate clock. Timing distortion errors due to uniform sampling of the low-rate PWM signals are reduced with the high forward loop gain of the digital modulator feedback loop. The driver receives a 22-bit digital audio input and combines the functionality of a high-fidelity digital-to-analog converter (DAC) with a speaker driver. It achieves 120 dB dynamic range over a 20 kHz bandwidth, provides 88% power efficiency while driving an 8 Ω speaker load, and consumes a total quiescent current of 2.4 mA.

A 120 dB Dynamic Range 400 mW Class-D Speaker Driver With Fourth-Order PWM Modulator

Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Xicheng Jiang

Papers

Phase interpolator device and method

Low frequency noise reduction circuit architecture for communications applications

High-speed serial data transceiver and related methods

A 120 dB Dynamic Range 400 mW Class-D Speaker Driver With Fourth-Order PWM Modulator

Methods and systems for adaptive receiver equalization