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Patent

High-speed serial data transceiver and related methods

Aaron Buchwald, +6 more
TLDR
In this article, a high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates.
Abstract: 
A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

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Citations
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Patent

Method and apparatus for evaluating and optimizing a signaling system

Jared L. Zerbe, +2 more
TL;DR: In this article, a method and apparatus for evaluating and optimizing a signaling system is described, in which a pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit.
Patent

Partial response receiver

Vladimir Stojanovic, +7 more
TL;DR: In this article, a signaling system consisting of a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device is described.
Patent

Clock recovery circuit

Masum Hossain, +2 more
TL;DR: In this article, a phase-locked loop (PLL) with two-point modulation is presented. But the linear phase-error signal is injected using an ultra-low latency delay path.
Patent

Adaptive equalization using correlation of edge samples with data patterns

Robert E. Palmer
TL;DR: In this article, an integrated receiver supports adaptive receive equalization, where an incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal, and some clock recovery circuitry adjusts the edge and clock signals as required to match their phases to the incoming data.
Patent

Low-power source-synchronous signaling

Jared L. Zerbe, +1 more
TL;DR: In this paper, the first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit devices, and the second device generates a timing signal based on transitions of the second signal.
References
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Journal ArticleDOI

The viterbi algorithm

Jr. G.D. Forney
TL;DR: This paper gives a tutorial exposition of the Viterbi algorithm and of how it is implemented and analyzed, and increasing use of the algorithm in a widening variety of areas is foreseen.
Journal ArticleDOI

Multicarrier modulation for data transmission: an idea whose time has come

J.A.C. Bingham
- 01 May 1990 - 
TL;DR: The general technique of parallel transmission on many carriers, called multicarrier modulation (MCM), is explained, and the performance that can be achieved on an undistorted channel and algorithms for achieving that performance are discussed.
Journal ArticleDOI

RSVP: a new resource ReSerVation Protocol

Lixia Zhang, +4 more
- 01 Sep 1993 - 
TL;DR: The resource reservation protocol (RSVP) as discussed by the authors is a receiver-oriented simplex protocol that provides receiver-initiated reservations to accommodate heterogeneity among receivers as well as dynamic membership changes.
Journal ArticleDOI

A scheme for real-time channel establishment in wide-area networks

Domenico Ferrari, +1 more
- 01 Apr 1990 - 
TL;DR: The results are judged encouraging: the approach satisfies the guarantees even in worst case situations, uses the network's resources to a fair extent, and efficiently handles channels with a variety of offered load and burstiness characteristics.
Journal ArticleDOI

Time interleaved converter arrays

W.C. Black, +1 more
TL;DR: In this article, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area.