Single-phase liquid cooled microchannel heat sink for electronic packages

In this paper, development of single-phase liquid cooling techniques for flip chip ball grid array packages (FBGAs) with high flux heat dissipations is reported. Two thermal test chips with different footprints, 12 mm/spl times/ 12 mm and 10 mm /spl times/10 mm, respectively, were used for high heat flux characterizations. A liquid-cooled aluminum heat sink with an area of 15 mm (L) /spl times/12.2 mm (W) populated by microchannels was designed and fabricated. The microchannel heat sink was assembled onto the chip, using a thermal interface material to reduce the contact thermal resistance at the interface. A variable speed pump was used to provide the pressure head for the liquid cooling loop. The measured thermal resistance results ranged from 0.44 to 0.32/spl deg/C/W for the 12-mm chip case and from 0.59 to 0.44/spl deg/C/W for the 10-mm chip case, both under flowrates ranging from 1.67/spl times/10/sup -6/ m/sup 3//s to 1.67/spl times/10/sup -5/ m/sup 3//s. An analytical model of the flow and heat transfer in microchannel heat sinks is also presented. Computational predictions agree with the measurements for pressure drop within 15% and thermal resistances within 6%. The analytical results indicate that thermal interface resistance becomes a key limitation to maximizing heat removal rate from electronic packages.

Development of liquid cooling techniques for flip chip ball grid array packages with High Heat flux dissipations

This paper demonstrates the application of computational fluid dynamic (CFD) simulation and response surface methodology (RSM) in analyzing the thermal performance of a high input/outputs, seven chips, indirect liquid cooled multichip module which will be applied in a kind of supercomputer. A series of similar experiments and corresponding CFD simulations are conducted firstly to evaluate the validity of CFD simulation method and determine the interfacial thermal resistance of thermal grease iteratively, and then a three-dimensional CFD model is established to investigate the heat transfer and fluid flow of the multichip module. Based on the CFD model, the individual effects of factors such as thermal conductivity of the thermal interface material and thermal grease, thickness of the chips, space between chips, solder bump patterns, solder ball patterns, flow velocity and liquid inlet temperature on the thermal performance of the module are studied with one-factor-at-a-time experimentation, and after that, four significant factors are selected to establish a response surface model of the maximum temperature of the module with central composite design based RSM and analysis of variance.

Thermal analysis for indirect liquid cooled multichip module using computational fluid dynamic simulation and response surface methodology

Too often, the effects of assembly process parameters are not sufficiently accounted for in the optimization of thermal interface performance. This becomes increasingly critical as demands on this performance continue to grow and alternative processes are developed. Notably, stencil printing is proving a competitive alternative to the traditional dispensing of thermal interface materials (TIMs), with potentially significant gains in units processed per hour (UPH) for some applications. The two techniques may, however, pose quite different challenges in terms of material flow, the resulting filler particle distribution and the risk of air bubble entrapment. Another part of the adhesive attachment process certain to affect void formation and growth, as well as possibly filler particle distribution, is the final cure. In addition, voids may severely reduce assembly robustness and reliability. The present work offers a discussion and a first case study to identify and illustrate voiding mechanisms for a particular TIM between a heat spreader and the back of a flip chip. Pronounced differences were observed between stencil printing and dispensing in terms of initial void formation, apparently related to the specific properties of the material. Measurements of the effects of heat ramp rate and peak temperature showed the subsequent evolution and final void size distribution to be determined by the initial part of the cure profile up to the material gelling temperature.

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Effects of assembly process variables on voiding at a thermal interface

Ensuring adequate thermal performance is essential for the reliable operation of flip-chip electronic packages. Thermal interface materials (TIMs), applied between the die and a heat spreader form a crucial thermal junction between the first level package and external cooling mechanisms such as heat-sinks and cooling fans. Selection of a good TIM is dependent not only on its thermal properties but also on its ability to withstand mechanical stresses in an electronic package. In the past, FEM models have been applied to obtain the stresses and strains in the TIM using time-independent analysis. However, there has only been limited work in extending these models to predict the damage (both mechanical and thermal) in a TIM during thermo-cyclic loading. Our current work presents a technique to predict the thermal damage in TIMs over cyclic loading. Calibrated finite element analysis models have been created to predict accurate TIM strains in thermal test-vehicles. These predicted mechanical strains are then correlated with experimentally observed thermal degradation and finally, a phenomenological model is developed which predicts the thermal performance of an electronic package during cyclic loading.

Predicting thermo-mechanical degradation of first-level thermal interface materials (TIMs) in flip-chip electronic packages

Industry demand for high power multi-chip packages is increasing to realize multifunctional compact systems. In line with industry requirements a multi-chip package suitable for high performance devices is developed. The package has 1296 I/Os. It is capable of handling 2 GHz signal speed and dissipating 75 W power with an external thermal solution. A concurrent design approach is adopted for the package design. Electrical, thermal, structural issues and assembly, and materials limitations are considered in developing this package. Package level thermal design challenges involve optimization of package structure and selection of stable thermal interface material. As a part of this project, a simulation model of the package along with the external thermal solution is developed and validated by measurements. The optimized heat spreader has been designed by performing a parametric study with the validated model. The type of thermal interface material (TIM) suitable to the package has also been identified by measurements. Desired thermal performance of the package has been achieved through design optimization of the package and selection of suitable TIM. Thermal modeling and measurement methodologies, validation and parametric study results are presented in the paper. Analysis of TIMs and measured thermal performance results of packages assembled with different type of TIMs are also discussed in the paper.

Xie Ling

Papers

Thermal design of heat spreader and analysis of thermal interface materials (TIM) for multi-chip package