Growing test data volume and excessive test power consumption in scan-based testing are both serious concerns for the semiconductor industry. Various test data compression (TDC) schemes and low-power X-filling techniques were proposed to address the above problems. These methods, however, exploit the very same “don't-care” bits in the test cubes to achieve different objectives and hence may contradict to each other. In this work, we propose a generic framework for test power reduction in linear decompressor-based test compression environment, which is able to effectively reduce shift-and capture-power simultaneously. Experimental results on benchmark circuits demonstrate that our proposed techniques significantly outperform existing solutions.

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On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment

In this paper, we present a new test data compression method for intellectual property (IP) cores testing, based on the reuse of parts of dictionary entries. Two approaches are investigated: the static and the dynamic. In the static approach, the content of the dictionary is constant during the testing of a core, while in the dynamic approach the testing of a core consists of several test sessions and the content of the dictionary is different during each test session. The efficiency of the proposed method is supported with extensive simulation results and comparisons to already known test data compression methods suitable for IP cores testing.

Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches

This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains

The paper deals with the problem of test data volume, test application time and on-chip test decompressor hardware overhead of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements. This paper presents a new test compression and test application approach that combines both the test pattern overlapping technique and the test pattern broadcasting technique. This new technique significantly reduces test application time by utilizing a new on-chip test decompressor architecture presented in this paper.

On test time reduction using pattern overlapping, broadcasting and on-chip decompression

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

Isometric Test Data Compression

IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both proportional to the number of test patterns N and the longest scan chain length L. To reduce test data volume and test cycle count, we can reduce N, L, or both. Earlier proposals focused on reducing the number of test patterns N through pattern compaction. All these proposals assume a 1-to-1 scan configuration, in which the number of internal scan chains equals the number of external scan I/O ports or test channels (two ports per channel) from ATE. Some have shown that ATPG for a circuit with multiple clocks using the multicapture clocking scheme, as opposed to one-hot clocking, generates a reduced number of test patterns.

Xinli Gu

Papers

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG