A bus for integrated circuits or embedded cores for serial access to circuits (e.g. for test, emulation, debug, trace operations) with limited pins. An integrated circuit (500) includes an IEEE 1149.1 Tap domain region (522) with Tap domains (502-508) having JTAQ circuits (510) coupled to an addressable Tap domain selection circuit (514) via buses (512). The selection circuit is coupled to a TDI input (520), a TCK input (516), a TMS input (518), and a TDO output (520).

Reduced signaling interface method & apparatus

Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Low power decompression of test cubes

Decompressors for low power decompression of test patterns

Scan testing and scan compression are key to realizing cost reduction and quality control of ever more complex designs. However, compression can be limited if the density of unknown (X) values is high. We present a method to identify a small, but important, subset of scan cells that are "likely" to capture an X, place them on separate "X-chains", create a combinational unload compressor tuned for these X-chains, and modify test generation to take advantage of this circuit. This method is fully integrated in the design-for-test (DFT) flow, requires no additional user input and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.

Increasing Scan Compression by Using X-chains

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Timing-aware test generation and fault simulation

IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both proportional to the number of test patterns N and the longest scan chain length L. To reduce test data volume and test cycle count, we can reduce N, L, or both. Earlier proposals focused on reducing the number of test patterns N through pattern compaction. All these proposals assume a 1-to-1 scan configuration, in which the number of internal scan chains equals the number of external scan I/O ports or test channels (two ports per channel) from ATE. Some have shown that ATPG for a circuit with multiple clocks using the multicapture clocking scheme, as opposed to one-hot clocking, generates a reduced number of test patterns.

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.

Method and apparatus for broadcasting test patterns in a scan-based integrated circuit

A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compiling 704 the RTL (register-transfer level) or Gate-Level HDL (hardware description language) code 701 based on the Input Constraints 702 and a Foundry Library 703 , into a Sequential Circuit Model 705 . The Sequential Circuit Model 705 is then transformed 706 into an equivalent Combinational Circuit Model 707 for performing Forward and/or Backward Clock Analysis 708 to determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model 707 . The analysis results are used for Uncontrollable/Unobservable Labeling 709 of selected inputs and outputs of the combinational logic gates. Finally, ATPG and/or Fault Simulation 710 are performed according to the Uncontrollable/Unobservable Labeling 709 to generate the HDL Test Benches and ATE Test Programs 711.

Method for performing ATPG and fault simulation in a scan-based integrated circuit

A method and apparatus for compacting test responses containing unknown values in a scan-based integrated circuit. The proposed X-driven compactor comprises a chain-switching matrix block and a space compaction logic block. The chain-switching matrix block switches the internal scan chain outputs before feeding them to the space compaction logic block for compaction so as to minimize X-induced masking and error masking. The X-driven compactor further selectively includes a finite-memory compaction logic block to further compact the outputs of the space compaction logic block.

Zhigang Wang

Papers

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

Method and apparatus for broadcasting test patterns in a scan-based integrated circuit

Method for performing ATPG and fault simulation in a scan-based integrated circuit

Compacting test responses using X-driven compactor

Method and apparatus for broadcasting scan patterns in a random access based integrated circuit