The pinned photodiode is the primary photodetector structure used in most CCD and CMOS image sensors. This paper reviews the development, physics, and technology of the pinned photodiode.

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A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect.

A Charge Transfer Model for CMOS Image Sensors

We discuss optimizations of pinned photodiode (PPD) pixels for indirect time of flight sensors. We focus on the transfer-gate and dumping gate regions optimization, on the PPD dimension and shape to assure fast lateral charge transfer and on the epitaxial layer thickness for a good tradeoff between fast vertical charge transfer and high quantum efficiency at near infrared region. The overall performance of the pixel is quantified by the demodulation contrast of the pixel at specific frequencies. The operation frequency of the device is determined by the required ambiguity range of the application and the required distance noise. In order to reach a reasonable distance noise, the pixel needs to allow modulation frequencies up to 100 MHz. In this paper, we present TCAD simulation and experimental data on demodulation contrast, impulse response time, and quantum efficiency of $10 \times 10\,\,\mu \text{m}$ pixels. We introduce a setup for impulse response measurement and we compare this to the demodulation contrast. We also discuss the optimization of the dump gate and dump diffusion. With the best pixel we measured a quantum efficiency of about 45% at 850 nm, a demodulation contrast of 47% at 80 MHz, and an impulse response time < 5 ns.

Optimization of Pinned Photodiode Pixels for High-Speed Time of Flight Applications

A 128-stage CMOS time delay integration (TDI) image sensor with on-chip digital accumulator was presented in this paper. By using two sets of sampling capacitors and an optimized timing, the on-chip column parallel cyclic analog-to-digital converter (ADC) in the sensor conducts the correlated double sampling, digital program gain amplifying, and A/D conversion all altogether in one ADC’s conversion time simultaneously. An on-chip digital accumulator suitable for this sensor is also proposed. A prototype $1024 \times 128$ CMOS TDI image sensor is fabricated in the 0.18- $\mu \text{m}$ CMOS technology, and the measurement results proof that the pixels and readout circuits in the sensor work properly. With a line rate of 3875 lines/s, the sensor costs a power consumption of 290 mW and a silicon area of $18.2~\textrm {mm}\times 18.9$ mm. The estimated maximum sensitivity of the fabricated sensor is 2010 $\textrm {V}/\textrm {lux}\cdot \textrm {sec}$ . This paper is suitable for applications in low-illumination, high scanning speed, and remote sensing systems.

A 128-Stage CMOS TDI Image Sensor With On-Chip Digital Accumulator

The limited dynamic range of conventional digital cameras is a well-known problem. A common solution is to apply high-dynamic-range (HDR) techniques over several images acquired using different exposure times. Time-of-flight (ToF) cameras using a photonic mixer device (PMD) are not an exception, since the dynamic range of its dual pixels is also limited. Furthermore, in this case, the saturation of the pixel channels leads to wrong depth measurements. An appropriate solution is the suppression of background illumination (SBI) system designed by the PMD. This system actually extends the dynamic range of the camera by hardware, but it also introduces noise when activated. In this paper, we present an adaptive HDR (AHDR) solution to the problem for the ToF case that overcomes the limited dynamic range of the system, allowing sensing along a theoretically infinite dynamic range with the only limitations of the power of the illumination system and the decay of the SNR with higher distances or lower illumination intensities. Our method is able to detect and segment relevant scene regions responsible for unexpected saturation, i.e., close foreground objects, from the rest of the scene and adjust the exposure times of the acquired images considering them. The results show a reduction in detail losses and a higher SNR in the AHDR raw images, with respect to single acquisitions. This results in a dramatic depth error reduction and effective axial resolution improvement in critical areas, while keeping a high frame rate. In addition, the SBI-related noise is eliminated.

Adaptive High Dynamic Range for Time-of-Flight Cameras

The charge transfer efficiency improvement method is introduced by optimizing the electrical potential distribution under the transfer gate along the charge transfer path. A non-uniform doped transfer transistor channel is introduced to provide an ascending electrical potential gradient in the transfer transistor channel. With the adjustments to the overlap length between the R1 region and the transfer gate, the doping dose of the R1 region, and the overlap length between the anti-punch-through (APT) implantations and transfer gate, the potential barrier and potential pocket in the connecting region of transfer transistor channel and the pinned photodiode (PPD) are reduced to improve the electrical potential connection. The simulation results show that the percentage of residual charges to total charges drops from 1/104 to 1/107, and the transfer time is reduced from 500 to 110 ns. This means the charge transfer efficiency is improved.

https://iopscience.iop.org/article/10.1088/1674-4926/33/12/124004/pdf

Charge transfer efficiency improvement of a 4-T pixel by the optimization of electrical potential distribution under the transfer gate

In order to increase collection efficiency and eliminate image lag, multi n-type implants were introduced into the process of a pinned-photodiode For the purpose of improving the collection efficiency, multi n-type implants with different implant energies were proposed, which expanded the vertical collection region To reduce the image lag, a horizontal gradient doping concentration eliminating the potential barrier was also formed by multi n-type implants The simulation result shows that the collection efficiency can be improved by about 10% in the long wavelength range and the density of the residual charge is reduced from 259 × 109 to 262 × 107cm−3

https://iopscience.iop.org/article/10.1088/1674-4926/32/12/124008/pdf

Collection efficiency and charge transfer optimization for a 4-T pixel with multi n-type implants

A wide-dynamic-range CMOS image sensor (CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion (FD) of a five-transistor active pixel is proposed With optimized pixel operation, the response curve is compressed and a wide dynamic range image is obtained A prototype wide-dynamic-range CMOS image sensor was developed with a 018 μm CIS process With the double exposure time 24 ms and 70 ns, the dynamic range of the proposed sensor is 80 dB with 30 frames per second (fps) The proposed CMOS image sensor meets the demands of applications in security surveillance systems

http://iopscience.iop.org/article/10.1088/1674-4926/31/5/055002/pdf

Wide dynamic range CMOS image sensor with in-pixel double-exposure and synthesis

A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size Based on the emission current theory, a qualitative photoresponse model is established to the preliminary prediction Further analysis of noise for incomplete charge transfer predicts the noise variation The test pixels were fabricated in a specialized 018 μm CMOS image sensor process and two different processes of buried N layer implantation are compared The trend prediction corresponds with the test results, especially as it can distinguish an unobvious incomplete charge transfer The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size

http://iopscience.iop.org/article/10.1088/1674-4926/34/5/054009/pdf

Analysis of incomplete charge transfer effects in a CMOS image sensor

A 10-bit ratio-independent switch-capacitor (SC) cyclic analog-to-digital converter (ADC) with offset canceling for a CMOS image sensor is presented. The proposed ADC completes an N-bit conversion in 1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversion characteristic of the proposed cyclic ADC is inherently insensitive both to capacitor ratio and to amplifier offset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18-μm one-poly four-metal CMOS technology. The measured results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 53.6 dB and a DNL of +0:12/−0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 μW with a 1.8 V supply, and its area is 0.03 × 0.8 mm2.

https://iopscience.iop.org/article/10.1088/1674-4926/35/3/035005/pdf

Xu Jiangtao

Papers

Charge transfer efficiency improvement of a 4-T pixel by the optimization of electrical potential distribution under the transfer gate

Collection efficiency and charge transfer optimization for a 4-T pixel with multi n-type implants

Wide dynamic range CMOS image sensor with in-pixel double-exposure and synthesis

Analysis of incomplete charge transfer effects in a CMOS image sensor

A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor