The pinned photodiode is the primary photodetector structure used in most CCD and CMOS image sensors. This paper reviews the development, physics, and technology of the pinned photodiode.

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A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect.

A Charge Transfer Model for CMOS Image Sensors

We discuss optimizations of pinned photodiode (PPD) pixels for indirect time of flight sensors. We focus on the transfer-gate and dumping gate regions optimization, on the PPD dimension and shape to assure fast lateral charge transfer and on the epitaxial layer thickness for a good tradeoff between fast vertical charge transfer and high quantum efficiency at near infrared region. The overall performance of the pixel is quantified by the demodulation contrast of the pixel at specific frequencies. The operation frequency of the device is determined by the required ambiguity range of the application and the required distance noise. In order to reach a reasonable distance noise, the pixel needs to allow modulation frequencies up to 100 MHz. In this paper, we present TCAD simulation and experimental data on demodulation contrast, impulse response time, and quantum efficiency of $10 \times 10\,\,\mu \text{m}$ pixels. We introduce a setup for impulse response measurement and we compare this to the demodulation contrast. We also discuss the optimization of the dump gate and dump diffusion. With the best pixel we measured a quantum efficiency of about 45% at 850 nm, a demodulation contrast of 47% at 80 MHz, and an impulse response time < 5 ns.

Optimization of Pinned Photodiode Pixels for High-Speed Time of Flight Applications

A 128-stage CMOS time delay integration (TDI) image sensor with on-chip digital accumulator was presented in this paper. By using two sets of sampling capacitors and an optimized timing, the on-chip column parallel cyclic analog-to-digital converter (ADC) in the sensor conducts the correlated double sampling, digital program gain amplifying, and A/D conversion all altogether in one ADC’s conversion time simultaneously. An on-chip digital accumulator suitable for this sensor is also proposed. A prototype $1024 \times 128$ CMOS TDI image sensor is fabricated in the 0.18- $\mu \text{m}$ CMOS technology, and the measurement results proof that the pixels and readout circuits in the sensor work properly. With a line rate of 3875 lines/s, the sensor costs a power consumption of 290 mW and a silicon area of $18.2~\textrm {mm}\times 18.9$ mm. The estimated maximum sensitivity of the fabricated sensor is 2010 $\textrm {V}/\textrm {lux}\cdot \textrm {sec}$ . This paper is suitable for applications in low-illumination, high scanning speed, and remote sensing systems.

A 128-Stage CMOS TDI Image Sensor With On-Chip Digital Accumulator

The limited dynamic range of conventional digital cameras is a well-known problem. A common solution is to apply high-dynamic-range (HDR) techniques over several images acquired using different exposure times. Time-of-flight (ToF) cameras using a photonic mixer device (PMD) are not an exception, since the dynamic range of its dual pixels is also limited. Furthermore, in this case, the saturation of the pixel channels leads to wrong depth measurements. An appropriate solution is the suppression of background illumination (SBI) system designed by the PMD. This system actually extends the dynamic range of the camera by hardware, but it also introduces noise when activated. In this paper, we present an adaptive HDR (AHDR) solution to the problem for the ToF case that overcomes the limited dynamic range of the system, allowing sensing along a theoretically infinite dynamic range with the only limitations of the power of the illumination system and the decay of the SNR with higher distances or lower illumination intensities. Our method is able to detect and segment relevant scene regions responsible for unexpected saturation, i.e., close foreground objects, from the rest of the scene and adjust the exposure times of the acquired images considering them. The results show a reduction in detail losses and a higher SNR in the AHDR raw images, with respect to single acquisitions. This results in a dramatic depth error reduction and effective axial resolution improvement in critical areas, while keeping a high frame rate. In addition, the SBI-related noise is eliminated.

Adaptive High Dynamic Range for Time-of-Flight Cameras

A single event upset (SEU) tolerant latch with a triple-interlocked structure is presented. Its self-recovery mechanism is implemented by using three pairs of guard-gates and inverters to construct feedback lines inside the structure. This latch effectively suppresses the effects of charge deposition at any single internal node caused by particle strikes. Three recently reported SEU-hardened latches are chosen and compared with this latch in terms of reliability. The potential problems that these three latches could still get flipped due to single event effects or single event effects plus crosstalk coupling are pointed out, which can be mitigated by this proposed latch. The SEU tolerance of each latch design is evaluated through circuit-level SEU injection simulation. Furthermore, discussions on the crosstalk robustness and some other characteristics of these latches are also presented.

An SEU-hardened latch with a triple-interlocked structure

A low reset noise CMOS image sensor (CIS) based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18 μm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6 μs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination.

http://iopscience.iop.org/article/10.1088/1674-4926/32/2/025012/pdf

Reset noise reduction through column-level feedback reset in CMOS image sensors

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented. This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel. Experimental results show the measured pinch-off voltage is consistent with theoretical prediction. This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sensor.

https://iopscience.iop.org/article/10.1088/1674-4926/31/7/074010/pdf

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor

A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed. This structure is based on associating two sets of two capacitors in cross series during the amplification phase. This circuit permits the common-mode voltage of the sample signal to reach full swing. Using the charge-complement technique, the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively. Simulation results show that as sample signal common-mode voltage changes, the difference between the minimum and maximum gain error is less than 0.03%. When the capacitor mismatch is increased from 0 to 0.2%, the gain error is deteriorated by 0.00015%. In all simulations, the gain of amplifier is 69 dB.

Xu Jiangtao

Papers

An SEU-hardened latch with a triple-interlocked structure

Reset noise reduction through column-level feedback reset in CMOS image sensors

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor

Switched-capacitor multiply-by-two amplifier with reduced capacitor mismatches sensitivity and full swing sample signal common-mode voltage

Research of MTF Velocity Mismatch Model for Time Delay Integration CMOS Area Image Sensors