The paper discusses the problem of testing multiple faults in combinational circuits. A definition of a test group is introduced for easier handling of fault masking. Test pair, as a known concept for proving correctness of a line in the circuit is regarded as a special case of the test group. A theorem is proved that if the test group will pass then a particular sub-circuit can be regarded as fault free at any possible combination of stuck-at-faults (SAF) in the circuit. Unlike the traditional approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit.

Multiple stuck-at-fault detection theorem

In this paper, we present the results of multiple-fault fault simulation experiments which have been performed on ISCAS combinational [I] and sequential [2] benchmarks. Using test sets generated by a single stuck-at fault test generator [3], we performed symbolic fault simulation to determine multiple stuck-at fault coverage. Injecting all faults simultaneously, our fault simulation algorithm uses N-ary decision diagrams (NDDs) to determine the effects of the faults on the behavior of the circuit. A testing function is generated by comparing the outputs computed by the faultfree circuit and the circuit with faults activated. The coverage is then determined by computing the ratio of the size of the satisfying set of the testing function and the number of possible multiple-fault scenarios.

Multiple-fault simulation and coverage of deterministic single-fault test sets

This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate test generation and reduce the number of test vectors generated, while higher fault coverage is derived. Experimental result for benchmark circuits shows the effectiveness of using the techniques. >

Efficient techniques for multiple fault test generation

Fault detection techniques using data compression methods have evolved during the last few years. Considerable work using individual Walsh spectral coefficients has been reported. In this paper, the application of spectral methods in testing of digital circuits with the emphasis on their usage for both input and output test compaction of digital circuits is described. Two closely related testing methods are discussed: syndrome testing and spectral testing as well as an overview of syndrome-testing and syndrome-testable design is presented. The necessary background and notation on Walsh spectral coefficients as well as their meaning in classical logic terms is shown.

/pdf/spectral-testing-of-digital-circuits-418szimrdj.pdf

Spectral Testing of Digital Circuits

A new approach to fault analysis is presented. The authors consider multiple stuck-at-0/1 faults at the gate level. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis the authors consider frontier faults where there is at least a normal path from each faulty line to a primary output. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, the authors evaluate the fault-free circuit and then propagate fault effects. Assuming that fault-free response is observed, a fault-dropping procedure is then applied to eliminate faulty conditions on lines, that are either absent or may be hidden by other faulty conditions. This method is applied to some benchmark circuits and achieves a high degree of efficiency. >

/pdf/use-of-fault-dropping-for-multiple-fault-analysis-17ogwtwvic.pdf

Use of fault dropping for multiple fault analysis

A method for analyzing multiple faults in gate-level combinational circuits that does not explicitly enumerate all the multiple stuck-at faults that may be present in a circuit is presented. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis, frontier faults where there is at least a normal path from each faulty line to a primary output are considered. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, the normal circuit is evaluated and the fault effects propagated. A fault dropping procedure is then applied to eliminate faulty conditions on specific lines that are either absent or permanently masked by other faulty conditions. The method is applied to some benchmark circuits, and significant speedup is observed. >

Multiple fault analysis using a fault dropping technique

A new method to generate test patterns for multiple stuck-at faults in combinational circuits is presented. All multiple faults of any multiplicity are assumed present in the circuit and one does not have to resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. The authors try to generate test conditions that propagate the effect of the target fault to primary outputs regardless the effects of other faults which might be present in the circuit. When these conditions are fulfilled, the input vector is a test for the target fault and for all multiple faults containing the target fault as component. The method used a branch-and-bound technique and includes several heuristics to enhance the performance and fault detection. Experiments performed on the ISCAS'85 benchmark circuits show that high fault coverage can be obtained at a reasonable increase in cost. >

/pdf/test-pattern-generation-for-multiple-stuck-at-faults-pgeiwzirb4.pdf

Y. Karkouri

Papers

Use of fault dropping for multiple fault analysis

Multiple fault analysis using a fault dropping technique

Test pattern generation for multiple stuck-at faults

Complexité du test des circuits logiques