Proceedings ArticleDOI
Multiple fault analysis using a fault dropping technique
A. Verreault,El Mostapha Aboulhamid,Y. Karkouri +2 more
- pp 162-169
TLDR
A method for analyzing multiple faults in gate-level combinational circuits that does not explicitly enumerate all the multiple stuck-at faults that may be present in a circuit is presented, and significant speedup is observed.Abstract:
A method for analyzing multiple faults in gate-level combinational circuits that does not explicitly enumerate all the multiple stuck-at faults that may be present in a circuit is presented. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis, frontier faults where there is at least a normal path from each faulty line to a primary output are considered. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, the normal circuit is evaluated and the fault effects propagated. A fault dropping procedure is then applied to eliminate faulty conditions on specific lines that are either absent or permanently masked by other faulty conditions. The method is applied to some benchmark circuits, and significant speedup is observed. >read more
Citations
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Proceedings ArticleDOI
Multiple-fault simulation and coverage of deterministic single-fault test sets
K. Kubiak,W.K. Fuchs +1 more
TL;DR: The results of multiple-fault fault simulation experiments which have been performed on ISCAS combinational and sequential benchmarks are presented and symbolic fault simulation to determine multiple stuck-at fault coverage is performed.
Journal ArticleDOI
Use of fault dropping for multiple fault analysis
TL;DR: A new approach to fault analysis is presented that considers multiple stuck-at-0/1 faults at the gate level using a fault collapsing phase and a fault-dropping procedure to eliminate faulty conditions on lines, that may be hidden by other faulty conditions.
Journal ArticleDOI
On the generation of test patterns for multiple faults
TL;DR: A new method to generate test patterns for multiple stuck-at faults in combinational circuits using similar techniques to those in FAN and SOCRATES algorithms to guide the search part of the algorithm, and includes several new heuristics to enhance the performance and fault detection capability.
Proceedings ArticleDOI
Gate-level timing verification using waveform narrowing
Jindrich Zejda,Eduard Cerny +1 more
TL;DR: A novel gate-level timing verification method that determines if a combinational circuit satisfies a maximal or a minimal required propagation delay, based on computing the greatest fixpoint over a set of equations derived from the gate forward and partial inverse functions, and their interconnections, in the domain of sets of waveforms.
Proceedings ArticleDOI
About robustness of test patterns regarding multiple faults
TL;DR: A new idea of test groups is presented as a general approach to generate test patterns for multiple stuck-at-faults in combinational circuits where each group has the goal to identify the correctness of a selected part of a circuit.
References
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Journal ArticleDOI
A method of fault analysis for test generation and fault diagnosis
H. Cox,Janusz Rajski +1 more
TL;DR: The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits using a 16-valued logic system, GEMINI, and an extended fault model which includes stuck-at, stuck-open, and delay faults is used.
Journal ArticleDOI
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
Abramovici,Breuer +1 more
TL;DR: The main vehicle of this approach is the deduction of internal line values in a circuit under test N*.
Journal ArticleDOI
Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
D.C. Bossen,Se June Hong +1 more
TL;DR: The theoretical results of this paper show that near minimal tests for multiple faults can be generated with complexity of computation comparable to that of single faults.
Proceedings ArticleDOI
A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits
F. Maamari,J. Rajski +1 more
TL;DR: The authors have delimited, for every convergent fanout stem, a region of the circuit outside of which the stem fault does not have to be simulated, and the fault simulation complexity of a circuit is shown to be directly related to the number and size of stem regions in the circuit.
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