Construction of porous interface on CNTs@NiCo-LDH core-shell nanotube arrays for supercapacitor applications

NiCoP nanowire@NiCo-layered double hydroxides nanosheet heterostructure for flexible asymmetric supercapacitors

One‐dimensional and two‐dimensional synergized nanostructures for high‐performing energy storage and conversion

Morphologically confined hybridization of tiny CoNi2S4 nanosheets into S, P co-doped graphene leading to enhanced pseudocapacitance and rate capability

In Situ Formation of Co 9 S 8 Quantum Dots in MOF-Derived Ternary Metal Layered Double Hydroxide Nanoarrays for High-Performance Hybrid Supercapacitors

Supercapacitors (SCs) have been widely studied as a class of promising energy-storage systems for powering next-generation E-vehicles and wearable electronics. Fabricating hybrid-types of electrode materials and designing smart nanoarchitectures are effective approaches to developing high-performance SCs. Herein, first, a Ni-Co selenide material (Ni,Co)Se2 with special cactus-like structure as the core, to scaffold the NiCo-layered double hydroxides (LDHs) shell, is designed and fabricated. The cactus-like structural (Ni,Co)Se2 core, as a highly conductive and robust support, promotes the electron transport as well as hinders the agglomeration of LDHs. The synergistic contributions from the two types of active materials together with the superior properties of the cactus-like nanostructure enable the (Ni,Co)Se2 /NiCo-LDH hybrid electrode to exhibit a high capacity of ≈170 mA h g-1 (≈1224 F g-1 ), good rate performance, and long durability. The as-assembled (Ni,Co)Se2 /NiCo-LDH//PC (porous carbon) asymmetric supercapacitor (ASC) with an operating voltage of 1.65 V delivers a high energy density of 39 W h kg-1 at a power density of 1650 W kg-1 . Therefore, the cactus-like core/shell structure offers an effective pathway to engineer advanced electrodes. The assembled flexible ASC is demonstrated to effectively power electronic devices.

(Ni,Co)Se2 /NiCo-LDH Core/Shell Structural Electrode with the Cactus-Like (Ni,Co)Se2 Core for Asymmetric Supercapacitors.

Rationally designing on sundry multiphase compounds has come into the spotlight for sodium-ion batteries (SIBs) due to enhanced structural stability and improved electrochemical performances. Nevertheless, there is still a lack of thorough understanding of the reaction mechanism of high-active phase boundaries existing between multiphase compounds. Here, a VS4 /Bi2 S3 @C composite anode for SIBs with rich phase boundaries in heterostructure is successfully synthesized. In situ X-ray diffraction analyses demonstrate a multistep redox mechanism in the heterostructures and ex situ transmission electron microscopy results confirm that tremendous self-generated phase boundaries are obtained and well-maintained during cycling, dramatically leading to stable reaction interfaces and better structural integrity. Combining experimental and theoretical results, a self-built-in electric field forming between phase boundaries acts as a dominate driving force for Na+ transport kinetics. Benefiting from the fast reaction kinetics of phase boundaries, the heterojunction provides an efficient approach to avoid abnormal voltage failure. As expected, the VS4 /Bi2 S3 @C heterostructure displays superior sodium storage performances, especially an excellent long-term cycling stability (379.0 mAh g-1 after 1800 cycles at a current density up to 2 A g-1 ). This work confirms a critical role of phase boundaries on superior reversibility and structural stability, and provides a strategy for analogous conversion/alloying-type anodes.

Rich Self-Generated Phase Boundaries of Heterostructured VS4 /Bi2 S3 @C Nanorods for Long Lifespan Sodium-Ion Batteries.

Layered Double Hydroxide Derived Cobalt-Iron Sulfide Heterostructures with Enhanced Reaction Kinetics for Use in Sodium-Ion Batteries

Ring voltage-controlled oscillator (VCO) based PLLs have several advantages over LC-VCO based PLLs, like smaller chip area, wider frequency tuning range and multi-phase output signals. However, the inferior jitter/phase noise of ring VCOs has always been the bottleneck of the overall PLL jitter/phase noise performance. To suppress ring VCO's phase noise, feedforward phase noise cancellation (FFPNC) techniques [1]–[4] and feedback phase noise cancellation (FBPNC) technique [5] are widely researched. However, most FFPNC and FBPNC based structures require numerous additional blocks, like complicated phase noise extraction circuits, long voltage-controlled delay line, or additional clock generation circuits, which consumes significant extra area and power. In order to suppress the phase noise of the ring VCO with minimal area and power consumption, this paper proposes a dual-path sub-sampling PLL (SSPLL) architecture incorporating an FBPNC technique. The SSPLL's bandwidth is extended with a compensated phase margin due to the proposed FBPNC technique, as a result, the in-band phase noise contributed by the ring VCO is effectively reduced.

A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression

This article presents a 2-GHz dual-path subsampling phase-locked loop (SSPLL) with ring voltage-controlled oscillator (VCO) phase noise suppression (PNS). In addition to the conventional subsampling charge pump (SSCP), a high-pass path from the subsampling phase detector (SSPD) to the low-pass filter (LPF) is implemented in the proposed SSPLL. Due to this dual-path architecture, a new in-band zero and pole are introduced into the open-loop transfer function (zero frequency is smaller than the pole frequency), which extends the open-loop unit-gain bandwidth without sacrificing the phase margin. Consequently, the phase noise contribution of the ring VCO is suppressed while the loop stability is ensured. Meanwhile, the phase noise contribution of the high-pass path is negligible compared to the reference and ring VCO’s contribution. Measurement results show that the SSPLL’s closed-loop bandwidth is extended to around 6 MHz with a reference of 20 MHz and the jitter is reduced by 1.34 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> (from 3.52 to 2.63 ps) with a maximum noise suppression of 6.5 dB at the 1.1-MHz offset. The PNS path consumes 0.16 mW and no delay line or calibration is needed, which results in a relatively high FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{PNC}}$</tex-math> </inline-formula> value of 40.5 dB. 

Yangtao Dong

Papers

(Ni,Co)Se2 /NiCo-LDH Core/Shell Structural Electrode with the Cactus-Like (Ni,Co)Se2 Core for Asymmetric Supercapacitors.

Rich Self-Generated Phase Boundaries of Heterostructured VS4 /Bi2 S3 @C Nanorods for Long Lifespan Sodium-Ion Batteries.

Layered Double Hydroxide Derived Cobalt-Iron Sulfide Heterostructures with Enhanced Reaction Kinetics for Use in Sodium-Ion Batteries

A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression

A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression