The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near- $V_{\rm T}$ ) or even to the subthreshold (sub- $V_{\rm T}$ ) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present and compare ReRAM-based Non-Volatile Flip-Flop (NVFF) topologies which are optimized for low-voltage operation (including near- $V_{\rm T}$ and sub- $V_{\rm T}$ operation). Three low-voltage NVFF circuit topologies are proposed and evaluated in terms of energy dissipation and reliability. Using topologies with two complementary programmed ReRAM devices, Monte Carlo simulations accounting for parametric variations confirm reliable data restore operation from the ReRAM devices at a sub- $V_{\rm T}$ voltage as low as 400 mV. A topology using a single ReRAM device exhibits lower write energy, but requires a near- $V_{\rm T}$ voltage for robust read. Energy characterization is performed at nominal, near- $V_{\rm T}$ , and sub- $V_{\rm T}$ supply voltages. The minimum energy point is reached for near- $V_{\rm T}$ read operation with a total read+write energy of 735 fJ.

/pdf/energy-reliability-trade-offs-in-low-voltage-reram-based-non-171fixdhu5.pdf

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors through memory generators, targeted at rather generic design specifications. As an alternative, standard cell memories (SCMs) can be defined, synthesized, and placed and routed as an integral part of a given digital system, providing complete design flexibility, good energy efficiency, low-voltage operation, and even area efficiency for small memory blocks. Yet implementing an SCM block with a standard digital flow often fails to exploit the distinct and regular structure of such an array, leaving room for optimization. In this article, we present a design methodology for optimizing the physical implementation of SCM macros as part of the standard design flow. This methodology introduces controlled placement, leading to a structured, noncongested layout with close to 100p placement utilization, resulting in a smaller silicon footprint, reduced wire length, and lower power consumption compared to SCMs without controlled placement. This methodology is demonstrated on SCM macros of various sizes and aspect ratios in a state-of-the-art 28nm fully depleted silicon-on-insulator technology, and compared with equivalent macros designed with the noncontrolled, standard flow, as well as with foundry-supplied SRAM macros. The controlled SCMs provide an average 25p reduction in area as compared to noncontrolled implementations while achieving a smaller size than SRAM macros of up to 1Kbyte. Power and performance comparisons of controlled SCM blocks of a commonly found 256 × 32 (1 Kbyte) memory with foundry-provided SRAMs show greater than 65p and 10p reduction in read and write power, respectively, while providing faster access than their SRAM counterparts, despite being of an aspect ratio that is typically unfavorable for SCMs. In addition, the SCM blocks function correctly with a supply voltage as low as 0.3V, well below the lower limit of even the SRAM macros optimized for low-voltage operation. The controlled placement methodology is applied within a full-chip physical implementation flow of an OpenRISC-based test chip, providing more than 50p power reduction compared to equivalently sized compiled SRAMs under a benchmark application.

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-V T ) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub-V T storage arrays and fill the gap of missing sub-V T memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D-latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220 mV) and a total energy of 14 fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65nm CMOS reported to date.

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-V T memory in 65nm CMOS

Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ultra-low-power (ULP) CS implementation is vital for these kind of energy-limited systems. Sub-threshold (sub-V T ) operation is commonly used for ULP computing, and can also be combined with CS. However, most established CS implementations can achieve either no or very limited benefit from sub-V T operation. Therefore, we propose a sub-V T application-specific instruction-set processor (ASIP), exploiting the specific operations of CS. Our results show that the proposed ASIP accomplishes 62x speed-up and 11.6x power savings with respect to an established CS implementation running on the baseline low-power processor.

/pdf/tamarisc-cs-an-ultra-low-power-application-specific-22051tsz1h.pdf

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V DD and V T to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V DD for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-μm test chip is used to compare normal sizing and sizing to minimize operational V DD and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.

Modeling and sizing for minimum energy operation in subthreshold circuits

Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-V T ) systems. First, two sub-V T analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-V T regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized at nominal supply voltage. Both analysis methods are able to predict the energy minimum supply voltage (EMV) of any given design. Next, the results of a sub-V T synthesis at EMV using re-characterized SCLs are compared to the initial synthesis results. Finally, the results of timing-driven synthesis in both the above-V T and the sub-V T domain are compared to the results of power-driven synthesis.

/pdf/synthesis-strategies-for-sub-v-t-systems-3c25wco4po.pdf

Synthesis strategies for sub-V T systems

A transceiver suitable for devices in wireless body area networks is presented. Stringent requirements are imposed by the high link loss between opposite sides of the body, about 85 dB in the 2.45 GHz ISM band. Despite this, minimum physical size and power consumption are required, and we target a transceiver with 1 mm2 chip area, 1 mW active power consumption, and data rate 250 kbit/s. The receiver is fully integrated., fabricated and measured in 65-nm CMOS, and size and power consumption are carefully considered at all levels of circuit and system design. The modulation is frequency shift keying, chosen because transmitters can be realized with high efficiency and low spurious emissions; a modulation index 2 creates a midchannel spectral notch. A direct-conversion receiver achieves minimum power consumption. A tailored demodulation structure makes the digital baseband compact and low power. The channel decoder has been implemented in both analog and digital domains to find the most power efficient solution. Antenna design and wave propagation are studied via simulations with phantoms. The 2.45 GHz ISM band was chosen as a good compromise between antenna size and link loss. An ultra-low power medium access scheme based on a duty-cycled wake-up receiver is designed.

Ultra low power transceivers for wireless sensors and body area networks

The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power.

A 0.28¿0.8V 320 fW D-latch for sub-VT memories in 65 nm CMOS

Reasons for facing knowledge diversity and mostly homogeneous groups among international students within international master programs generally and more specifically at LTH have been discussed. In order to reduce the knowledge differences, teachers have to acknowledge this diversity as a first step. Different approaches and solutions for organizing an international master program within an international environment have been proposed. The suggested approaches exploit the students cultural and academic diversity and adjust the programs policies step by step from students’ pre-admission to post-admission, pre-arrival and interaction during courses. Interaction amongst heterogenous student groups have been highlighted as key factor for achieving a substantial international education. Different approaches to encourage students to interact with each other have been discussed. Suggestions have been proposed on how to design course task in a suitable way, including cultural and education information about individual student. Moreover, approaches for initializing interaction among heterogeneous student groups have been presented. Suitable ways on how to provide students with guidance on group work have been discussed, helping students to efficient work together and exploit their cultural diversities. The necessity of reflection has been emphasized, in order to build substantial, culturally diverse, experiences and benefit from international teaching and learning.

Yasser Sherazi

Papers

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-V T memory in 65nm CMOS

Synthesis strategies for sub-V T systems

Ultra low power transceivers for wireless sensors and body area networks

A 0.28¿0.8V 320 fW D-latch for sub-VT memories in 65 nm CMOS

Diversity in International Master Programss - Knowledge differences and group dynamics