Y
Yasuhisa Shimazaki
Researcher at Renesas Electronics
Publications - 46
Citations - 1072
Yasuhisa Shimazaki is an academic researcher from Renesas Electronics. The author has contributed to research in topics: Integrated circuit & Low-power electronics. The author has an hindex of 17, co-authored 45 publications receiving 1054 citations. Previous affiliations of Yasuhisa Shimazaki include Keio University.
Papers
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Proceedings ArticleDOI
Low-power embedded SRAM modules with expanded margins for writing
Masanao Yamaoka,Noriaki Maeda,Yoshihiro Shinozaki,Yasuhisa Shimazaki,Koji Nii,Shigeru Shimada,Kazumasa Yanagisawa,Takayuki Kawahara +7 more
TL;DR: In this article, a low-power embedded SRAM module implements a writing margin expansion for lowvoltage operation, a write replica circuit for low power operation and a lowleakage structure.
Journal ArticleDOI
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
Masanao Yamaoka,Yoshihiro Shinozaki,Noriaki Maeda,Yasuhisa Shimazaki,K. Kato,Shigeru Shimada,Kazumasa Yanagisawa,K. Osadal +7 more
TL;DR: In this paper, an on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed, which supports three operating modes - high-speed active mode, low-leakage low-speed activity mode, and standby mode - and uses a subdivisional power-line control (SPC) scheme.
Proceedings ArticleDOI
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM
Kiichi Niitsu,Yasuhisa Shimazaki,Yasufumi Sugimori,Yoshinori Kohama,Kazutaka Kasuga,Itaru Nonomura,Makoto Saen,Shigenobu Komatsu,Kenichi Osada,Naohiko Irie,Toshihiro Hattori,Atsushi Hasegawa,Tadahiro Kuroda +12 more
TL;DR: This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling, and all the bits of the SRAM is successfully accessed with no bit error under changes of supply voltages and temperature.
Proceedings ArticleDOI
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor
Toshihiro Hattori,T. lrita,Masayuki Ito,Eiji Yamamoto,Hiromu Kato,G. Sado,Y. Yamada,Kunihiko Nishiyama,H. Yagi,T. Koike,Y. Tsuchihashi,M. Higashida,Hiroyuki Asano,I. Hayashibara,Ken Tatezawa,Yasuhisa Shimazaki,Naozumi Morino,K. Hirose,Saneaki Tamaki,S. Yoshioka,R. Tsuchihashi,N. Arai,T. Akiyama,K. Ohno +23 more
TL;DR: A power-management scheme for a single-chip multi-CPU processor uses 20 power domains and enables the minimization of leakage currents in each operating mode: 299muA in paging operation and 7 muA in stand-by.
Proceedings ArticleDOI
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor
Yusuke Kanno,Hiroyuki Mizuno,Y. Yasu,K. Hirose,Yasuhisa Shimazaki,Tadashi Hoshi,Y. Miyairi,T. lshii,Tetsuya Yamada,Takahiro Irita,T. Hattori,Kazumasa Yanagisawa,N. lrie +12 more
TL;DR: Hierarchical power distribution with a power tree has been developed and leakage currents of a 1,000,000-gate power domain were effectively reduced to 1/4,000 in multi-CPU SoCs with minimal area overhead.