M
Masayuki Ito
Researcher at Renesas Electronics
Publications - 27
Citations - 437
Masayuki Ito is an academic researcher from Renesas Electronics. The author has contributed to research in topics: Multi-core processor & System on a chip. The author has an hindex of 12, co-authored 27 publications receiving 437 citations.
Papers
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Journal ArticleDOI
A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS
TL;DR: A 6-bit 3.5-GS/s flash ADC with interpolation factor optimized considering random offset, active area, and systematic offset to realize low offset and small active area is reported.
Proceedings ArticleDOI
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor
Toshihiro Hattori,T. lrita,Masayuki Ito,Eiji Yamamoto,Hiromu Kato,G. Sado,Y. Yamada,Kunihiko Nishiyama,H. Yagi,T. Koike,Y. Tsuchihashi,M. Higashida,Hiroyuki Asano,I. Hayashibara,Ken Tatezawa,Yasuhisa Shimazaki,Naozumi Morino,K. Hirose,Saneaki Tamaki,S. Yoshioka,R. Tsuchihashi,N. Arai,T. Akiyama,K. Ohno +23 more
TL;DR: A power-management scheme for a single-chip multi-CPU processor uses 20 power domains and enables the minimization of leakage currents in each operating mode: 299muA in paging operation and 7 muA in stand-by.
Proceedings ArticleDOI
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler
Masayuki Ito,Toshihiro Hattori,Yoichi Yoshida,K. Hayase,Tomoichi Hayashi,Osamu Nishii,Y. Yasu,Atsushi Hasegawa,M. Takada,Hiroyuki Mizuno,Kunio Uchiyama,Toshihiko Odaka,Jun Shirako,Masayoshi Mase,Keiji Kimura,Hironori Kasahara +15 more
TL;DR: This work develops an SoC with 8 processor cores and 8 user RAMs targeted for power-efficient high-performance embedded applications and assigns 16 blocks to separate power domains so that they can be independently be powered off.
Proceedings ArticleDOI
A 45nm 37.3GOPS/W heterogeneous multi-core SoC
Yoichi Yuyama,Masayuki Ito,Yoshikazu Kiyoshige,Yusuke Nitta,Shigezumi Matsui,Osamu Nishii,Atsushi Hasegawa,Makoto Ishikawa,Tetsuya Yamada,Junichi Miyakoshi,Koichi Terada,Tohru Nojiri,Makoto Satoh,Hiroyuki Mizuno,Kunio Uchiyama,Yasutaka Wada,Keiji Kimura,Hironori Kasahara,Hideo Maejima +18 more
TL;DR: A heterogeneous multi-core SoC for applications, such as digital TV systems with IP networks (IP-TV) including image recognition and database search, and automatic parallelization compilers analyze parallelism of the data flow, generate coarse grain tasks, and schedule tasks to minimize execution time considering data transfer overhead for general-purpose CPU and FE.
Patent
Data processing device
TL;DR: In this article, a plurality of ways are selected from among the ways according to a value of select data created based on tag address information which is part of address information, and cache tags are read.