A large amount of work world-wide has been directed towards obtaining an understanding of the fundamental characteristics of porous Si. Much progress has been made following the demonstration in 1990 that highly porous material could emit very efficient visible photoluminescence at room temperature. Since that time, all features of the structural, optical and electronic properties of the material have been subjected to in-depth scrutiny. It is the purpose of the present review to survey the work which has been carried out and to detail the level of understanding which has been attained. The key importance of crystalline Si nanostructures in determining the behaviour of porous Si is highlighted. The fabrication of solid-state electroluminescent devices is a prominent goal of many studies and the impressive progress in this area is described.

The structural and luminescence properties of porous silicon

It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

http://nathan.instras.com/documentDB/paper-44.pdf

Surface photovoltage phenomena: theory, experiment, and applications

http://nathan.instras.com/documentDB/paper-69.pdf

Porous silicon: a quantum sponge structure for silicon based optoelectronics

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

Photoluminescence (PL) spectra and decay dynamics were studied for the spontaneously oxidized porous Si with subsequent various thermal annealing procedures. The PL decay was highly nonexponential and well described by the stretched‐exponential function. The PL lifetime was shorter for the higher PL photon energy, but at the same photon energy it decreased by an order of magnitude by the thermal annealing in N2 gas, in parallel with the large PL intensity decrease. This PL quenching upon the annealing is presumably ascribable to both the structural changes and dangling bond formations in porous Si, as suggested by ESR measurements and the annealing experiments in H2 gas.

Effects of thermal annealing on porous silicon photoluminescence dynamics

We present a new threshold-voltage (Vth) control technique for fully-silicided (FUSI) metal/high-k gate stacks which are suitable for 45nm-node LOP and LSTP CMOS. The key is the phase control of FUSI Ni-silicide by changing Ni film thickness prior to silicidation anneal. As a result, Ni/sub 3/Si and NiSi/sub 2/ are formed whose effective workfunctions (WFs) on HfSiON are found to be 4.8eV and 4.4eV, respectively, being largely displaced from Si-midgap by /spl plusmn/0.2eV. Meanwhile, the dopant segregation method, known to be successful in Vth-control of NiSi on SiO/sub 2/, did not work on HfSiON. With Ni/sub 3/Si-PMOS and NiSi/sub 2/-NMOS transistors, a wide range of Vth-tuning is achieved coping with both LSTP and LOP requirements. At the same time, leakage suppression merit is better than the 45nm-node targets at electrical thickness (Tinv) around 2.0 nm. Also, our phase-controlled fully silicided (PC-FUSI) devices show excellent mobility characteristics.

Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices

Precise control of pn-junction profiles for GaN-based LD structures using GaN substrates with low dislocation densities

A field control electrode 9 is formed over an insulating film 6 on a channel layer 2, between a gate electrode 5 and a drain electrode 8. Tantalum oxide (Ta2 O5), for example, may be used as the material for the insulating film 6.

Fet having non-overlapping field control electrode between gate and drain

Luminescent properties of anodized porous Si are experimentally investigated. An extremely long decay time together with a peculiar temperature dependence due to the competing Auger process are observed for the visible luminescence band indicating an analogous recombination mechanism to that of electron-hole pairs being trapped at spatially separated tail states in a-Si:H. Besides this visible luminescence, an intense emission is also detected in the infrared region around 1.1 eV. Its decay time is shorter than that of the visible band and possible recombination mechanisms are discussed

Yasunori Mochizuki

Papers

Effects of thermal annealing on porous silicon photoluminescence dynamics

Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices

Precise control of pn-junction profiles for GaN-based LD structures using GaN substrates with low dislocation densities

Fet having non-overlapping field control electrode between gate and drain

Luminescent properties of visible and near-infrared emissions from porous silicon prepared by the anodization method.