This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed back for phase detection in a phase-locked loop. Third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator. A prototype of the proposed frequency generator is implemented in digital 40 nm CMOS. It exhibits a PN of $-100\;\text{dBc/Hz}$ at 1 MHz offset from 57.8 GHz and provides 25% frequency tuning range (TR). The achieved figure-of-merit (FoM) is between 179 and 182 dBc/Hz.

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A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier

This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 μm integrated circuits, which have a combined active area of 0.06 mm 2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

A W-band wide locking range injection-locked frequency tripler (ILFT) with low dc power consumption is presented in this paper. By using a transformer coupled (TC) topology, the proposed TC-ILFT features the following advantages: 1) the negative resistance of the cross-coupled pair is not degraded due to the proposed TC-ILFT without source degeneration, and the TC-ILFT can be operated in lower dc supply voltage as compared to the conventional ILFTs; 2) the dc bias of the injector can be properly designed for maximizing locking range; 3) the parasitic capacitance provided by the injector can be reduced due to the impedance transformation; and 4) the larger device size of the injector can be chosen enhancing the third harmonic. Moreover, the operation frequency and the locking range of this work are boosted using a multiorder resonator. A theoretical model of the proposed TC-ILFT is also established and it has been carefully verified with the experimental results. The free-running oscillation frequency of the proposed TC-ILFT is 94.51 GHz. As the input power is -1 dBm, the measured locking range is 5.9 GHz without varactor tunning. The dc supply voltage and the power consumption are 0.7 V and 1 mW, respectively.

A W-Band Wide Locking Range and Low DC Power Injection-Locked Frequency Tripler Using Transformer Coupled Technique

A compact balanced frequency doubler with more than 35 dB odd-harmonic rejection and fractional bandwidth of 73% is presented in this letter. Wide bandwidth and high odd-harmonic suppression is achieved by adopting a new technique for the transformer balun design, resulting in a very low magnitude imbalance of 0.13 dB and a phase imbalance of 0.4° over 7–15 GHz. The balun performance is improved by offsetting the radius of the primary and secondary coils, which reduces the parasitic coupling capacitance. The input and output frequency ranges for the doubler are 7–15 GHz and 14–30 GHz respectively. The circuit was fabricated in 0.13- $\mu \text{m}$ SiGe technology. The chip size is 0.6 mm $\times \, 0.4$ mm.

A $K$ -Band Frequency Doubler With 35-dB Fundamental Rejection Based on Novel Transformer Balun in 0.13- $\mu \text{m}$ SiGe Technology

This paper presents two D-band frequency quadruplers (FQs) employing different circuit techniques. First FQ is a 129–171-GHz stacked Gilbert-cell multiplier using a bootstrapping technique, which improves the bandwidth and the conversion gain with respect to the conventional topology. Stacked architecture enables current reuse for the second frequency doubler resulting in a compact and energy-efficient design. The circuit reaches 3-dB bandwidth of 42 GHz, which is the highest among similar reported quadruplers. It achieves 2.2-dBm saturated output power, 5-dB peak conversion gain, and 1.7% peak DC-to-RF efficiency. The stacked FQ occupies 0.08 mm2 and consumes 22.7 mA from 4.4-V supply. Second presented circuit is a transformer-based injection-locked FQ (T-ILFQ) employing an E-band push–push voltage-controlled oscillator (PP-VCO). The VCO is a self-buffered common-collector Colpitts oscillator with a transformer formed on emitter inductors. Proposed configuration does not reduce the tuning range of the VCO, thus providing wide locking range and high sensitivity with respect to the injected signal. The T-ILFQ achieves 21.1% locking range, which is the highest among other reported injection-locked frequency multipliers. The peak output power is −4 dBm and the input sensitivity reaches −22 dBm. The circuit occupies 0.09 mm2 and consumes 14.8 mA from 3.3-V supply.

D-Band Frequency Quadruplers in BiCMOS Technology

In this paper, we present design and analysis of an innovative low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked phase-locked loop (PLL) with self-aligned delay-locked loop in 65-nm CMOS technology With the proposed innovative topology, the phase between the injection signal and the voltage-controlled oscillator in the PLL can be dynamically aligned to minimize the jitter over the variations A modified theoretical model of the sub-harmonically injection-locked PLL with self-aligned injection is developed for the design methodology The in-band phase noise of the sub-harmonically injection-locked PLL can be significantly improved using the self-aligned sub-harmonically injection-locked technique The design considerations of the locking range, loop bandwidth, and frequency division ratio are addressed At 10 GHz, the measured phase noise of the proposed PLL with self-aligned injection at 1-MHz offset is -1302 dBc/Hz with a root-mean-square jitter of 44 fs The total dc power consumption is 627 mW From 10 °C to 70 °C, the measured phase noise at 1-MHz offset and jitter are better than -129 dBc/Hz and 48 fs, respectively This work demonstrates excellent performance and good robustness over the variations, and it can be compared to the previously reported state-of-the-art sub-harmonically injection-locked PLLs

A Low-Jitter Low-Phase-Noise 10-GHz Sub-Harmonically Injection-Locked PLL With Self-Aligned DLL in 65-nm CMOS Technology

In this paper, we present design and analysis of a W-band divide-by-three injection-locked frequency divider (ILFD) in 90 nm CMOS process. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for W -Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than -15 dBm. The core dc power consumption is 1.5 mW with a supply voltage of 0.7 V.

Design and Analysis of a $W$ -band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique

An injection-locked frequency divider (ILFD) including a signal injector, an oscillator (OSC), and a buffer stage is provided. The signal injector is configured for receiving an injection signal. The OSC is configured for dividing the frequency of the injection signal, so as to generate a first divided frequency signal, where there is an integral-multiple relation between the frequency of the first divided frequency signal and that of the injection signal. The buffer stage is configured for receiving and boosting the first divided frequency signal, and performing a push-push process on the first divided frequency signal, so as to output a second divided frequency signal, where there is a fractional-multiple relation between the frequency of the second divided frequency signal and that of the injection signal.

Injection-locked frequency divider

A Ka-band monolithic high-efficiency frequency quadrupler using a GaAs heterojunction bipolar transistor and pseudomorphic high electron-mobility transistor technology is presented in this paper. The frequency quadrupler is constructed cascading two frequency doublers. The frequency doubler employs a modified common-base/common-source topology to enhance the second harmonic efficiently. The dc bias condition, harmonic output power, conversion gain, and efficiency for variable configurations are investigated. Two phase-shifter networks are used to reduce phase error and improve the fundamental rejection. Between 23-30 GHz, the proposed frequency quadrupler features a conversion gain of higher than -1 dB with an input power of 4 dBm. The maximum conversion gain is 2.7 dB at 28 GHz with an efficiency of up to 8% and a power-added efficiency of 3.6%. The maximum output 1-dB compression point (P1 dB) and the saturation output power (Psat) are higher than 7 and 8.2 dBm, respectively. The overall chip size is 2×1 mm2.

Yen-Liang Yeh

Papers

A W-Band Wide Locking Range and Low DC Power Injection-Locked Frequency Tripler Using Transformer Coupled Technique

A Low-Jitter Low-Phase-Noise 10-GHz Sub-Harmonically Injection-Locked PLL With Self-Aligned DLL in 65-nm CMOS Technology

Design and Analysis of a $W$ -band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique

Injection-locked frequency divider

Design and Analysis of a $Ka$ -Band Monolithic High-Efficiency Frequency Quadrupler Using GaAs HBT–HEMT Common-Base/Common-Source Balanced Topology