International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

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Performance evaluation and design trade-offs for network-on-chip interconnect architectures

The Internet of Things (IoT) is entering the daily operation of many industries; applications include but are not limited to smart cities, smart grids, smart homes, physical security, e-health, asset management, and logistics. For example, the concept of smart cities is emerging in multiple continents, where enhanced street lighting controls, infrastructure monitoring, public safety and surveillance, physical security, gunshot detection, meter reading, and transportation analysis and optimization systems are being deployed on a city-wide scale. A related and cost-effective user-level IoT application is the support of IoT-enabled smart buildings. Commercial space has substantial requirements in terms of comfort, usability, security, and energy management. IoT-based systems can support these requirements in an organic manner. In particular, power over Ethernet, as part of an IoT-based solution, offers disruptive opportunities in revolutionizing the in-building connectivity of a large swath of devices. However, a number of deployment-limiting issues currently impact the scope of IoT utilization, including lack of comprehensive end-to-end standards, fragmented cybersecurity solutions, and a relative dearth of fully-developed vertical applications. This paper reviews some of the technical opportunities offered and the technical challenges faced by the IoT in the smart building arena.

IoT Considerations, Requirements, and Architectures for Smart Buildings—Energy Optimization and Next-Generation Building Management Systems

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.

Survey of low-power testing of VLSI circuits

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SoC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SoC as well as an industrial SoC.

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Test wrapper and test access mechanism co-optimization for system-on-chip

Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.

Testing 3D chips containing through-silicon vias

Today's complex SoCs need sophisticated infrastructure IP, not only to test and diagnose embedded memories but also to repair them and improve fabrication yield. The authors solution integrates memory IP with test and repair IP in a composite infrastructure IP that ensures manufacturing and field repair efficiency and optimizes SoC yield.

Embedded-memory test and repair: infrastructure IP for SoC yield

Today's system-on-chip typically embeds memory IP cores with very large aggregate bit count per SoC. This trend requires using dedicated resources to increase memory yield, while containing test and repair cost and minimizing time-to-volume. This paper summarizes the evolution of such yield optimization resources, compares their trade-offs, and concentrates on on-chip infrastructure IP. To maximize the repair efficiency, this infrastructure IP needs to leverage the memory design knowledge and the process failure data. The ideal solution is to integrate the memory IP and its infrastructure IP into a single composite IP that yields itself effectively.

Embedded memory test and repair: infrastructure IP for SOC yield

Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to update their knowledge on memories. This hot topic paper provides an embedded tutorial on embedded memories, in terms of what is new and coming versus what is old and vanishing, and what are the associated design, test, and repair challenges related to using embedded memories.

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Challenges in Embedded Memory Design and Test

System chips are increasingly designed by embedding reusable cores. A core-based test strategy for such ICs is often attractive and sometimes even mandatory. IEEE P1500 SECT is a standard under development that standardizes a core test language and a core wrapper, in order to facilitate plug-n-play core testing. In this paper, we describe how one standard supports both easy integration and interoperability as well as flexibility and scalability. Possible usage scenarios of the standard for core providers, core users, and EDA tool developers are sketched.

Yervant Zorian

Papers

Testing 3D chips containing through-silicon vias

Embedded-memory test and repair: infrastructure IP for SoC yield

Embedded memory test and repair: infrastructure IP for SOC yield

Challenges in Embedded Memory Design and Test

On using IEEE P1500 SECT for test plug-n-play