Showing papers by "Yihwan Kim published in 2006"
Patent•
12 Dec 2006TL;DR: In this paper, the formation of the epitaxial layer involves exposing a substrate in a process chamber to deposition gases including two or more silicon sources such as silane and a higher order silane.
Abstract: Methods for formation of epitaxial layers containing silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the epitaxial layer involves exposing a substrate in a process chamber to deposition gases including two or more silicon source such as silane and a higher order silane. Embodiments include flowing dopant source such as a phosphorus dopant, during formation of the epitaxial layer, and continuing the deposition with the silicon source gas without the phosphorus dopant.
74 citations
Patent•
30 Jun 2006TL;DR: In this paper, a method for processing a substrate including a pre-cleaning etch and reduced pressure process is described, which involves introducing a substrate into a processing chamber, flowing an etching gas into the processing chamber; processing at least a portion of the substrate with the etching gases to remove a contaminated or damaged layer from a substrate surface; stopping flow of the etch gas; evacuating the process chamber to achieve a reduced pressure in the chamber; and processing the substrate surface at the reduced pressure.
Abstract: A method for processing a substrate including a pre-cleaning etch and reduced pressure process is disclosed. The pre-cleaning process involves introducing a substrate into a processing chamber; flowing an etching gas into the processing chamber; processing at least a portion of the substrate with the etching gas to remove a contaminated or damaged layer from a substrate surface; stopping flow of the etching gas; evacuating the processing chamber to achieve a reduced pressure in the chamber; and processing the substrate surface at the reduced pressure. Epitaxial deposition is then used to form an epitaxial layer on the substrate surface.
28 citations
TL;DR: In this paper, a low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy process for advanced transistor fabrications was developed, which demonstrated elevated source/drain formation on ultra-thin (30 %) and [B] (> 2E20 cm-3) concentrations, and selective Si:c epitaxy with high substitutional C concentration (> 1 %).
Abstract: We have developed low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (≤ 700 °C), we have demonstrated elevated source/drain formation on ultra-thin ( 30 %) and [B] (>2E20 cm-3) concentrations, and selective Si:C epitaxy with high substitutional C concentration (>1 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters by adapting non-conventional deposition method.