Showing papers in "IEEE Electron Device Letters in 2017"

$\beta$ -Ga2O3 MOSFETs for Radio Frequency Operation

Abstract: We demonstrate a $\beta $ -Ga2O3 MOSFET with record-high transconductance ( ${g}_{m}$ ) of 21 mS/mm and extrinsic cutoff frequency ( ${f}_{T}$ ) and maximum oscillating frequency ( ${f}_{\max }$ ) of 3.3 and 12.9 GHz, respectively, enabled by implementing a new highly doped ohmic cap layer with a sub-micron gate recess process. RF performance was further verified by CW Class-A power measurements with passive source and load tuning at 800 MHz, resulting in ${P}_{{OUT}}$ , power gain, and power-added efficiency of 0.23 W/mm, 5.1 dB, and 6.3%, respectively. These preliminary results indicate potential for monolithic or heterogeneous integration of power switch and RF devices using $\beta $ -Ga2O3.

High-Performance Depletion/Enhancement-ode $\beta$ -Ga2O3 on Insulator (GOOI) Field-Effect Transistors With Record Drain Currents of 600/450 mA/mm

Abstract: In this letter, we report on high-performance depletion/enhancement-mode $\beta $ -Ga2O3 on insulator (GOOI) field-effect transistors (FETs) with record high drain currents ( $\text{I}_{\mathrm {\sf D}}$ ) of 600/450 mA/mm, which are nearly one order of magnitude higher than any other reported $\text{I}_{\mathrm {\sf D}}$ values. The threshold voltage ( $\text{V}_{\mathrm {\sf T}}$ ) can be modulated by varying the thickness of the $\beta $ -Ga2O3 films and the E-mode GOOI FET can be simply achieved by shrinking the $\beta $ -Ga2O3 film thickness. Benefiting from the good interface between $\beta $ -Ga2O3 and SiO2 and wide bandgap of $\beta $ -Ga2O3, a negligible transfer characteristic hysteresis, high $\text{I}_{\mathrm {\sf D}}$ ON/OFF ratio of $10^{10}$ , and low subthreshold swing of 140 mV/decade for a 300-nm-thick SiO2 are observed. E-mode GOOI FET with source to drain spacing of 0.9- $\sf \mu \text{m}$ demonstrates a breakdown voltage of 185 V and an average electric field (E) of 2 MV/cm, showing the great promise of GOOI FET for future power devices.

High-Performance GaN Vertical Fin Power Transistors on Bulk GaN Substrates

Abstract: This letter reports a GaN vertical fin power field-effect-transistor structure with submicron fin-shaped channels on bulk GaN substrates. In this vertical transistor design only n-GaN layers are needed, while no material regrowth or p-GaN layer is required. A combined dry/wet etch was used to get smooth fin vertical sidewalls. The fabricated transistor demonstrated a threshold voltage of 1 V and specific on resistance of 0.36 ${\mathrm {m}}\Omega {\mathrm {cm}}^{2}$ . By proper electric field engineering, 800 V blocking voltage was achieved at a gate bias of 0 V.

HfZrO x -Based Ferroelectric Synapse Device With 32 Levels of Conductance States for Neuromorphic Applications

Abstract: We propose a HfZrO x (HZO)-based ferroelectric synapse device with multi-levels states of remnant polarization that is equivalent to multi-levels conductance states. By optimizing the pulse condition, we obtained 32 levels of remnant polarization states for both potentiation and depression. Furthermore, a ferroelectric field-effect transistor is simulated using the obtained multiple remnant polarization states. The simulation results show that linear and symmetric conductance states can be obtained by applying optimum potentiation and depression pulse conditions. A neural network was simulated using the proposed devices for pattern recognition. Using synapse parameters of the HZO-based ferroelectric device and a neural network simulator, we have confirmed that the pattern recognition accuracy of the MNIST data set is 84%. It shows that the HZO-based synapse device has potential for future high-density neuromorphic systems.

Improving Analog Switching in HfO x -Based Resistive Memory With a Thermal Enhanced Layer

Abstract: Analog RRAM with hundreds of resistance levels is an attractive device for neuromorphic computing. However, it is still very challenging to realize good analog behavior in filamentary RRAM cells. In this letter, we developed a novel methodology to improve the analog switching in filamentary RRAM. The impact of local temperature on analog switching behavior is elucidated. The transition from abrupt switching to analog switching is found at higher temperature. Based on this result, a thermal enhanced layer (TEL) is proposed to confine heat in switching layer for realizing analog RRAM. The HfO x /TEL RRAM shows analog switching characteristics with more than ten times window using 50-ns pulses. Finally, a 1-kb analog RRAM array is demonstrated with uniform analog switching, fast speed, excellent resistance window, and excellent retention properties.

First Demonstration of Ga 2 O 3 Trench MOS-Type Schottky Barrier Diodes

Abstract: We developed $\beta $ -Ga2O3 trench MOS-type Schottky barrier diodes (MOSSBDs) for the first time A Si-doped Ga2O3 layer was grown via halide vapor phase epitaxy on a single-crystal Sn-doped $\beta $ -Ga2O3 (001) substrate The trench structure was fabricated using dry etching and photolithography HfO2 film was used as the dielectric film of the trench MOS structure The specific on-resistances ( ${R} _{{ \mathrm{ON},\mathsf {SP}}}$ ) of the normal SBD and trench MOSSBD were about 23 and 29 $\text{m}\Omega $ cm $^{{\mathsf {2}}}$ , respectively The reason the ${R} _{{ \mathrm{ON},\mathsf {SP}}}$ of MOSSBD was a little higher than that of the Schottky barrier diodes (SBD) is that the current path decrease as a result of forming the trench MOS structure The normal SBD had a large reverse leakage current due to the large electric field at the anode metal/semiconductor interface On the other hand, the trench MOSSBD had several orders of magnitude smaller leakage current We, thus, demonstrated that incorporating the trench MOS structure in Ga2O3 is highly effective for decreasing the reverse leakage current

Ge-Doped ${\beta }$ -Ga2O3 MOSFETs

Abstract: We report on MOSFETs fabricated on Ge-doped $\beta $ -Ga2O3 homoepitaxial material grown by molecular beam epitaxy on (010) Fe-doped semi-insulating substrates. The Ge-doped channel devices performed similar to previously reported devices with Sn- and Si-doped channels with the drain current ON/OFF ratios of $> 10^{8}$ and the saturated drain current of >75 mA/mm at $V_{G}=0$ V. Hall effect measurements showed a high carrier mobility of 111 cm2/( $\text{V}\cdot \text{s}$ ) with $4\times 10^{17}$ cm $^{-3}$ active carriers. A MOSFET with a gate-drain spacing of $5.5~\mu \text{m}$ had a three-terminal breakdown voltage of 479 V.

Normally-Off C–H Diamond MOSFETs With Partial C–O Channel Achieving 2-kV Breakdown Voltage

Abstract: Diamond has unique physical properties, which show great promise for applications in the next generation power devices. Hydrogen-terminated (C–H) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) often have normally-on operation in devices, because the C–H channel features a p-type inversion layer; however, normally-off devices are preferable in power MOSFETs from the viewpoint of fail safety. We fabricated hydrogen-terminated (C–H) diamond MOSFETs using a partially oxidized (partial C–O) channel. The fabricated MOSFETs showed a high breakdown voltage of over 2 kV at room temperature and normally-off characteristics with a gate threshold voltage $\text{V}_{\mathrm{th}}$ of −2.5–−4 V.

Implementing p-bits With Embedded MTJ

Abstract: Magnetic tunnel junctions (MTJs) utilizing unstable magnets with low barriers have been shown to be well-suited for the implementation of random number generators (RNGs). It has recently been shown that completely new applications involving optimization, inference, and invertible Boolean logic would be enabled if many RNGs can be interconnected to form large scale correlated networks. However, this requires a new device, namely, a three-terminal tunable RNG or a p-bit, whose input terminal can be used to pin its output to 0 or 1. In this letter, we show that a voltage driven p-bit can be implemented simply by incorporating existing RNGs into a transistor circuit using experimentally demonstrated 2-terminal MTJs, without requiring a new device. Using established SPICE models, we show that this proposed p-bit can be interconnected to build correlated p-circuits to implement useful functionalities including a representative example of an invertible AND gate that “factors” the output of an AND gate into consistent input combinations.

Phosphorene: A Promising Candidate for Highly Sensitive and Selective SF 6 Decomposition Gas Sensors

Abstract: Phosphorene is a promising candidate for gas sensing materials. This letter describes our study of the adsorption of SF6 and SF6 decomposition gases (SO2 and H2 S) on phosphorene. We used first principles calculations to explore phosphorene’s potential applications as gas sensor to diagnose the state of online gas insulated switchgear (GIS). The calculation results showed that only the adsorption of SO2 induced a moderate adsorption energy and apparent charge transfer. We further investigated the current–voltage ( ${I}$ – ${V}$ ) relationships before and after gas absorption through the non-equilibrium Green’s function method. It was found that only SO2 induced a dramatic change in the ${I}$ – ${V}$ relationships. Therefore, phosphorene appears to be a promising candidate for highly sensitive and selective SF6 decomposition gas sensors for online GIS diagnosis.

In Situ O xide, G aN Interlayer-Based Vertical Trench MOS FET ( OG-FET ) on Bulk GaN substrates

Abstract: In this letter, we report on high breakdown voltage in situ oxide, GaN interlayer-based vertical trench MOSFETs (OG-FETs) on bulk GaN substrates. Following our previous work on OG-FETs on GaN on sapphire, utilizing a low damage gate-trench etch and using bulk GaN substrates, a breakdown voltage of 990 V with an on-resistance 2.6 $\text{m}\Omega ~\cdot $ cm2, was achieved. Without edge termination, a high breakdown field of 1.6 MV/cm was achieved in these devices.

Vertical GaN Junction Barrier Schottky Rectifiers by Selective Ion Implantation

Abstract: This letter demonstrates vertical GaN junction barrier Schottky (JBS) rectifiers fabricated with novel ion implantation techniques. We used two different methods to form the lateral p-n grids below the Schottky contact: 1) Mg implantation into n-GaN to form p-wells and 2) Si implantation into p-GaN to form n-wells. Specific differential ON-resistances ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of 1.5–2.5 $\text{m}\Omega ~\cdot $ cm2 and 7–9 $\text{m}\Omega ~\cdot $ cm2 were obtained in the Mg-implanted and Si-implanted JBS rectifiers, respectively. A breakdown voltage of 500–600 V was achieved in both devices, with a leakage current at high reverse biases at least 100-fold lower than conventional vertical GaN Schottky barrier diodes. The impact of n-well and p-well widths on the ${R}_{ \mathrm{\scriptscriptstyle ON}}$ and BV was investigated. Fast switching capability was also demonstrated. This letter shows the feasibility of forming patterned p-n junctions by novel ion implantation techniques, to enable high-performance vertical GaN power devices.

High Breakdown Voltage (−201) $\beta $ -Ga2O3 Schottky Rectifiers

Abstract: $\beta $ -Ga2O3 Schottky barrier diodes were fabricated in a vertical geometry structure consisting of Ni/Au rectifying contacts without edge termination on Si-doped epitaxial layers ( $10~\mu \text{m}$ , $\text{n}\sim 4\times 10^{15}$ cm $^{-3})$ on Sn-doped bulk Ga2O3 substrates with full-area Ti/Au back Ohmic contacts The reverse breakdown voltage, ${V} _ \text {BR}$ , was a function of rectifying contact area, ranging from 1600 V at $31\times 10^{-6}$ cm2 (20- $\mu \text{m}$ diameter) to ~250 V at $22{\times }10^{-3}$ cm $^{-2}$ (053-mm diameter) The current density near breakdown was not strongly dependent on contact circumference but did scale with contact area, indicating that the bulk current contribution was dominant The lowest ON-state resistance, ${R} _\text {on}$ , was 16 $\text{m}\Omega \cdot $ cm2 for the largest diode and 25 $\text{m}\Omega \cdot $ cm2 for the 1600-V rectifier, leading to a Baliga figure-of-merit ( ${V} _\text {BR}^{2}/{R} _\text {on})$ for the latter of approximately 1024 MW $\cdot $ cm $^{-2}$ The ON-OFF ratio was measured at a forward voltage of 13 V and ranged from $3\times 10^{7}$ to $25\times 10^{6}$ for reverse biases from −5 to −40 V and showed only a small dependence on temperature in the range from 25 °C to 100 °C

Investigation of the p-GaN Gate Breakdown in Forward-Biased GaN-Based Power HEMTs

Abstract: In this letter, we report a detailed experimental investigation of the time-dependent breakdown induced by forward gate stress in GaN-based power HEMTs with a p-type gate, controlled by a Schottky metal/p-GaN junction. When a high stress voltage is applied on the gate, a large voltage drop and an electric field occur in the depletion region of the p-GaN close to the metal interface, promoting the formation of a percolation path. We have investigated the mechanisms underlying the gate breakdown by adopting different stress conditions, analyzing the influence of the temperature, and investigating the activation energy of the traps. In addition, thanks to this approach, the device lifetime has been evaluated and an original empirical model, representing the relationship between the gate leakage current and the time to failure, has been proposed.

Emulating Short-Term and Long-Term Plasticity of Bio-Synapse Based on Cu/a-Si/Pt Memristor

Abstract: Short-term plasticity and long-term plasticity of bio-synapse are thought to underpin critical physiological functions in neural circuits. In this letter, we vividly emulated the short-term and long-term synaptic functions in a single Cu/a-Si/Pt memristor. By controlling the injection quantity of Cu cations into the a-Si layer, the device showed volatile and non-volatile resistive switching behaviors. Owing to the unique characteristics of Cu/a-Si/Pt device, the short-term synaptic functions, i.e., short-term potentiation, pair-pulse facilitation, and long-term functions, i.e., long-term potentiation/depression, spike-timing-dependent plasticity, were mimicked in the memristor successfully. Furthermore, the transition from short-term memory to long-term memory of the device was also observed under repeated stimuli. The experimental results confirm that the Cu/a-Si/Pt memristor with various synaptic behaviors has a potential application in the brain-inspired computing systems.

Ga 2 O 3 MOSFETs Using Spin-On-Glass Source/Drain Doping Technology

Abstract: We report the first demonstration of source/drain (S/D) doping using tin (Sn) doped spin-on-glass (SOG) on Ga2O3 power MOSFET. The effectiveness of SOG doping is verified by a comparative experiment on semi-insulating Ga2O3 substrates. A specific contact resistance of $\rho _{c}= 2.1\pm 1.4\times 10^{-5}\,\,\Omega \cdot $ cm2 is obtained to the SOG doped layer. The thermal diffusion behavior of Sn in Ga2O3 is investigated as well. MOSFETs with SOG S/D doping is fabricated on 200-nm epitaxial Ga2O3 layer with an average effective doping of $2\times 10^{17}$ /cm3. An increased peak output drain current density of 40 mA/mm is achieved due to reduced S/D resistance. The maximum transconductance (gm) is extracted to be 1.23 mS/mm for a device with $\mathrm{L_g}= 2 \mu \text{m}$ . The device also shows a large ON/ OFF ratio of $10^{8}$ and breakdown voltage of 382 V.

Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V

Abstract: In this letter, an n-type short-channel negative capacitance FinFET (NC-FinFET) with a hysteresis window of 0.48 V, an on-/off-current ratio of 107, and a sub-20-mV/decade average subthreshold slope (SSavg) that is intended to overcome the Boltzmann limit (i.e., the physical limit in the SS, which is 60 mV/decade at 300 K), is experimentally demonstrated vs. a baseline FinFET with an SSavg of ~105 mV/decade. In our testing, we confirmed that the large hysteresis window in a short-channel NC-FinFET can be suppressed by using an appropriate source/drain extension length ( $\text {L}_{\text {ext}})$ . As $\text {L}_{\text {ext}}$ in the NC-FinFET is increased, the gate-to-source/drain capacitance ( $\text {C}_{\text {GS}}/\text {C}_{\text {GD}})$ decreased and the hysteresis window narrows.

First Principles Investigation of Small Molecules Adsorption on Antimonene

Abstract: The gas-adsorption behaviors of the pristine antimonene are investigated by first principles calculations to exploit its potential for high-performance gas sensing. The results show that the atmospheric gas molecules (N2, CO2, O2, and H2O) presented ubiquitously in the sensing environments weakly bind to antimonene, while the polluted gas adsorbates (NH3, SO2, NO, and NO2) show stronger affinity toward antimonene with considerable adsorption energies and elevated charge transfers. Considering the susceptibility of the electronic properties of antimonene induced by the adsorbed molecules, we suggest that single-layered antimonene could be an eligible sensing material for polluted gases detection.

Demonstration of 4H-SiC Digital Integrated Circuits Above 800 °C

Abstract: Short-term demonstrations of packaged 4H-SiC junction field-effect transistor (JFET) logic integrated circuits (ICs) at temperatures exceeding 800 °C in air are reported, including a 26-transistor 11-stage ring oscillator that functioned at 961 °C ambient temperature believed unprecedented for electrical operation of a semiconductor IC. The expanded temperature range should assist temperature acceleration testing/qualification of such ICs intended for long-term use in applications near 500 °C ambient, and perhaps spawn new applications. Ceramic package assembly leakage currents inhibited the determination of some intrinsic SiC device/circuit performance properties at these extreme temperatures, so it is conceivable that even higher operating temperatures might be obtained from SiC JFET ICs by employing packaging and circuit design intended/optimized for T $\ge800$ °C.

Functionally Complete Boolean Logic in 1T1R Resistive Random Access Memory

Abstract: Nonvolatile stateful logic through RRAM is a promising route to build in-memory computing architecture. In this letter, a logic methodology based on 1T1R structure has been proposed to implement functionally complete Boolean logics. Arbitrary logic functions could be realized in two steps: initialization and writing. An additional read step is required to read out the logic result, which is in situ stored in the nonvolatile resistive state of the memory. Cascade problem in building larger logic circuits is also discussed. Our 1T1R logic device and operation method could be beneficial for massive integration and practical application of RRAM-based logic.

An On-Chip Bandpass Filter Using a Broadside-Coupled Meander Line Resonator With a Defected-Ground Structure

Abstract: An on-chip bandpass filter (BPF) is designed and fabricated in a 0.13- $\mu \text{m}$ SiGe (Bi)-CMOS technology. This BPF consists of a broadside-coupled meander-line resonator (BCMLR) in conjunction with a defected-ground structure (DGS). By simply grounding a BCMLR, the resonator can be converted into a BPF. Further applying a DGS to this BPF, an additional transmission zero can be generated in the high-frequency band. To understand the fundamentals of this design, an $LC$ -equivalent circuit is given for investigation of the transmission zeros and poles. The measured results show that the BPF has a center frequency at 33 GHz with a bandwidth of 18%. The minimum insertion loss is 2.6 dB, while the maximum stopband attenuation is 44 dB. The chip size, excluding the pads, is only 0.038 mm2 ( $0.126\times0.3$ mm $^{2}$ ).

Effect of Tensile and Compressive Bending Stress on Electrical Performance of Flexible a-IGZO TFTs

Abstract: We report the changes in device performance of flexible amorphous indium-gallium-zinc-oxide thin-film transistors (TFTs) by 1.65% tensile or compressive bending stress for 10 k times. The TFTs exhibit negative threshold voltage ( $\Delta {V}_{\sf Th}$ ) shift and enhanced drain current ( ${I}_{D}$ ). TFT performance under repetitive tensile bending stress exhibits comparatively large threshold voltage shift ( $\Delta {V}_{\sf Th} = - {\sf 2.3}$ V) than compressive bending stress ( $\Delta {V}_{\sf Th}= - 0.9$ V), which might be originated from both the generation of interface states ( ${N}_{\sf int})$ and gap trap density (dN $_{\sf gap}$ /dE) by $3.5\times 10^{11}$ /cm2 and $5.7\times 10^{12}$ /cm2 eV, respectively under tensile bending stress. These are much higher than those ( ${N}_{\sf int}$ : $1.2\times 10^{11}$ /cm2 and dN $_{\sf gap}$ /dE: $2.2\times 10^{12}$ /cm2eV) for compressive bending. The increase in the DOS appears after both types of the bending stress which is related to the generation of oxygen vacancies. According to technology computer aided design simulation, the 10 k times repetitive compressive bending stress generates donor like states ( $\Delta {N}_{\sf GD}) \sim 2\times 10^{16}$ cm $^{-3}$ and tensile bending stress generates $\Delta {N}_{\sf GD} \sim 9.5\times 10^{16}$ cm $^{-3}$ at $\sim {E} _{C} -0.35$ eV.

200 V Enhancement-Mode p-GaN HEMTs Fabricated on 200 mm GaN-on-SOI With Trench Isolation for Monolithic Integration

Abstract: Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electron mobility transistors with a gate width of 36 mm are achieved This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size

High-Performance 500 V Quasi- and Fully-Vertical GaN-on-Si pn Diodes

Abstract: This letter demonstrates quasi- and fully vertical GaN-on-Si pn diodes with record performance. The optimized device structure employs a highly conductive (N D >10 20 cm -3 ) current collecting layer and a lightly carbon-doped drift layer. With this optimization, a differential specific on-resistance (R ON ) of 0.8-1 mΩ·cm 2 , a breakdown voltage (BV) over 500 V, and a high forward current (~kA/cm 2 ) were demonstrated. Excellent R ON and BV performance up to 300 °C were also obtained. A small reverse recovery time of 50 ns was demonstrated under switching conditions. With Baliga's figure of merit over 0.32 GW/cm 2 , these devices show the great potential of low-cost GaN-onSi vertical devices for future power applications.

Linking Conductive Filament Properties and Evolution to Synaptic Behavior of RRAM Devices for Neuromorphic Applications

Abstract: We perform a comparative study of HfO2 and Ta2O5 resistive switching memory (RRAM) devices for their possible application as electronic synapses. By means of electrical characterization and simulations, we link their electrical behavior (digital or analog switching) to the properties and evolution of the conductive filament (CF). More specifically, we identify that bias-polarity-dependent digital switching in HfO2 RRAM is primarily related to the creation and rupture of an oxide barrier. Conversely, the modulation of the CF size in Ta2O5 RRAM allows bias-polarity-independent analog switching with multiple states. Therefore, when the Ta2O5 RRAM is used to implement a synapse in multilayer perceptron neural networks operated by back-propagation algorithms, patterns in handwritten digits can be recognized with high accuracy.

Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf 0.8 Zr 0.2 O 2 , High Endurance and Breakdown Recovery

Abstract: We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of $>10^{10}$ read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.

N-Polar GaN Cap MISHEMT With Record Power Density Exceeding 6.5 W/mm at 94 GHz

Abstract: A novel N-Polar GaN cap (MIS)high electron mobility transistor demonstrating record 6.7-W/mm power density with an associated power-added efficiency of 14.4% at 94 GHz is presented. This state-of-the-art power performance is enabled by utilizing the inherent polarization fields of N-Polar GaN in combination with a 47.5-nm in situ GaN cap layer to simultaneously mitigate dispersion and improve access region conductivity. These excellent results build upon past work through the use of optimized device dimensions and a transition from a sapphire to a substrate for reduced self-heating.

Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM

Abstract: We compare the performance of static random access memory (SRAM) cells based on negative capacitance (NC) FinFETs and reference FinFETs at the 7-nm technology node. We use a physics-based model for NC FinFETswhere we couple the Landau–Khalatnikovmodel of ferroelectric materials with the standard BSIM-CMG model of FinFET. For the reference FinFETs, we use the predictive model parameters optimized for SRAM design as per the ASAP7 PDK. We exploit the unique characteristics of NC-FinFETs and demonstrate that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.

Sulfur Dioxide and Nitrogen Dioxide Gas Sensor Based on Arsenene: A First-Principle Study

Abstract: Properties of sulfur dioxide (SO2) and nitrogen dioxide (NO2) adsorbed on different types of arsenenes (pristine, boron-, and nitrogen-doped arsenene) are studied with the first-principle approach, which is based on the density functional theory. Adsorption energy, adsorption distance, Hirshfeld charge, and I–V characteristic are calculated. The results demonstrate that NO2 and SO2 exhibit a chemisorption character on boron-doped arsenene (B-arsenene) while a physisorption character on pristine and nitrogen-doped arsenene (P- and N-arsenene) with moderate adsorption energy. Moreover, analysis of density of state shows a positive change of electronic property when the two gas molecules are adsorbed on pristine/doped arsenenes. According to the I–V characteristic curves, N-arsenene can be treated as an excellent sensing material for SO2 gas sensor. Meanwhile, P-arsenene has a potential application in the NO2 gas sensor.

Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics

Abstract: In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently. An experimental NC-FinFET device is accurately modeled and the experimentally calibrated parameters are used to analyze the NC-FinFETs device performance and its dependence on several key parameters.