Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

http://chialvo.org/Curso/UBACurso/DIA7/Papers/Aono_NatMat_07_Ionic%20Switching%20Memory.pdf

Nanoionics-based resistive switching memories

The primary metric for gauging progress in the various semiconductor integrated circuit technologies is the spacing, or pitch, between the most closely spaced wires within a dynamic random access memory (DRAM) circuit. Modern DRAM circuits have 140 nm pitch wires and a memory cell size of 0.0408 mum(2). Improving integrated circuit technology will require that these dimensions decrease over time. However, at present a large fraction of the patterning and materials requirements that we expect to need for the construction of new integrated circuit technologies in 2013 have 'no known solution'. Promising ingredients for advances in integrated circuit technology are nanowires, molecular electronics and defect-tolerant architectures, as demonstrated by reports of single devices and small circuits. Methods of extending these approaches to large-scale, high-density circuitry are largely undeveloped. Here we describe a 160,000-bit molecular electronic memory circuit, fabricated at a density of 10(11) bits cm(-2) (pitch 33 nm; memory cell size 0.0011 microm2), that is, roughly analogous to the dimensions of a DRAM circuit projected to be available by 2020. A monolayer of bistable, [2]rotaxane molecules served as the data storage elements. Although the circuit has large numbers of defects, those defects could be readily identified through electronic testing and isolated using software coding. The working bits were then configured to form a fully functional random access memory circuit for storing and retrieving information.

A 160-kilobit molecular electronic memory patterned at 10 11 bits per square centimetre

Memory effects are ubiquitous in nature and are particularly relevant at the nanoscale where the dynamical properties of electrons and ions strongly depend on the history of the system, at least within certain time scales. We review here the memory properties of various materials and systems which appear most strikingly in their non-trivial, time-dependent resistive, capacitative and inductive characteristics. We describe these characteristics within the framework of memristors, memcapacitors and meminductors, namely memory-circuit elements with properties that depend on the history and state of the system. We examine basic issues related to such systems and critically report on both theoretical and experimental progress in understanding their functionalities. We also discuss possible applications of memory effects in various areas of science and technology ranging from digital to analog electronics, biologically inspired circuits and learning. We finally discuss future research opportunities in the field.

Memory effects in complex materials and nanoscale systems

A significant performance limitation in integrated circuits has become the metal interconnect, which is responsible for depressing the on-chip data bandwidth while consuming an increasing percentage of power. These problems will grow as wire diameters scale down and the resistance-capacitance product of the interconnect wires increases hyperbolically, which threatens to choke off the computational performance increases of chips that we have come to expect over time. We examine some of the quantitative implications of these trends by analyzing the International Technology Roadmap for Semiconductors. We compare the potential of replacing the global electronic interconnect of future chips with a photonic interconnect and see that there is in principle a four order of magnitude bandwidth-to-power ratio advantage for the latter. This indicates that it could be possible to dramatically improve chip performance without scaling transistors but rather utilize the capability of existing transistors much more efficiently. However, at this time it is not clear if these advantages can be realized. We discuss various issues related to the architecture and components necessary to implement on-chip photonic interconnect.

Nanoelectronic and Nanophotonic Interconnect

Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.

Nanowire-based programmable architectures

We have developed a process to fabricate a cross-bar structure using UV-curable nanoimprint lithography with a UV-curable double-layer spin-on resist, metal lift off and Langmuir–Blodgett film deposition. This process allowed us to produce 1-kbit cross-bar memory circuits at 30-nm half-pitch on both top and bottom electrodes. Read, write, erase and cross talking were also investigated.

/pdf/one-kilobit-cross-bar-molecular-memory-circuits-at-30-nm-46dsbsqiy4.pdf

One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography

A method and mold for creating nanoscale patterns in an ion-selective polymer membrane is provided, in which a mold comprising a substrate and a molding layer having at least one protruding feature is imprinted on the ion-selective polymer membrane, thereby creating a recessed feature in the membrane. Protruding features having nanoscale dimensions can be created, e.g., by using self-assembled nanostructures as a shadow mask for etching a molding layer. In one embodiment, an imprinted ion selective polymer membrane, suitable for use as a solid electrolyte, is adapted for use in an electrochemical device or fuel cell by adding a metal catalyst to one portion of the membrane to serve as a catalytic electrode.

Imprinting nanoscale patterns for catalysis and fuel cells

A technique involving two steps of chemical mechanical polishing (CMP) has been developed to produce ultra-smooth metal surfaces with an RMS roughness better than 0.1 nm. A figure of merit termed degree of smoothness (DOS) is proposed for the purpose of quantifying the extent of smoothness of a polished metal surface. A post CMP metal slurry cleaning solution was used for cleaning Pt slurry for the first time and by applying special techniques, a very high quality clean surface was attained. Applications of the polished Pt electrodes in interfacing molecular switching devices with self-assembled monolayers of molecules have been found to dramatically improve the packing and orientation of the molecular monolayer with a huge improvement in the molecular electronics device yields. These smooth metal surfaces may open doors for new opportunities in future nanoscale devices.

/pdf/ultra-smooth-platinum-surfaces-for-nanoscale-devices-4pndjslj6b.pdf

Ultra-smooth platinum surfaces for nanoscale devices fabricated using chemical mechanical polishing

Memristive devices are promising building blocks for enhanced CMOS hardware in data storage and computing. Nanoimprint lithography (NIL) has been an enabling technology in the past decade for exploring novel devices and circuits. In this paper, the authors review the progress and technical aspects of the fabrication and integration of memristor crossbar arrays using NIL. Since the key component of successful fabrication is the imprint mold, the material selection, master mold fabrication, anti-sticking treatment and cleaning are first discussed. The requirements and composition of imprint resists, in particular low-viscosity liquid resists that cross-link upon ultraviolet light radiation, are investigated next. After the description of imprint systems and alignment mechanisms, a disruptive self-alignment fabrication scheme for crossbar arrays is presented. Finally, the first implementation of a memristor/CMOS hybrid circuit using NIL on foundry-made CMOS substrates, together with more recent developments, is recounted. The challenges and possible solutions for NIL as a primary tool for crossbar fabrication are also proposed and discussed.

Yong Chen

Papers

One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography

Imprinting nanoscale patterns for catalysis and fuel cells

Ultra-smooth platinum surfaces for nanoscale devices fabricated using chemical mechanical polishing

Nanoimprint lithography enables memristor crossbars and hybrid circuits