This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverter-based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB.

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

In this article, a 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign–sign least-mean-squares (SSLMS) algorithm is applied to adaptation for not only a decision feedback equalizer (DFE) but also a continuous-time linear equalizer (CTLE) to unify the adaptation methods. This approach facilitates concurrent adaptation that results in short adaptation time and also reduces the extra hardware and power consumption. An average value of fourth- and fifth-post-cursors is used as an indicator for CTLE adaptation, and the validity is substantiated by numerical analysis and simulation. Furthermore, the concept of a biased data-level reference (dLev) is proposed and analyzed to alleviate insufficient adaptation of the SSLMS algorithm in the presence of pre-cursor inter-symbol interference (ISI). The proposed dLev is acquired by simply adjusting up and down ratios of the dLev update equation. The prototype test chip is implemented in 65-nm CMOS technology and occupies an active area of 0.174 mm2. The proposed adaptive equalizers compensate for the channel loss of up to 34 dB at 10.8 Gb/s. Total power consumption of the receiver is 37.2 mW at 10.8 Gb/s, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.1 pJ/b/dB is achieved.

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

Intelligent driving system requires more precise and reliable steering control, and steering-by-wire (SBW) technology can better adapt to the development of autonomous driving. The permanent magnet synchronous motor (PMSM) servo system is the actuator of the SBW. Aiming at the uncertainties of the PMSM servo system, a new adaptive control method for the PMSM servo system is proposed. Parameter adaptive laws are designed for each slowly varying parameter and unknown parameter, and robust terms are introduced to the adaptive laws for the parameter uncertainties. The convergence speed of the parameter adaptive law proposed can be improved by adjusting the parameters related to the convergence rate. To reduce the scope of disturbance uncertainties, the steering load disturbances are divided into a bounded unknown time-varying part and a predictable time-varying disturbance. Based on the Luenberger observer, the prediction term of the load torque is estimated by the current of PMSM in real time. By introducing boundary estimation and robust term of unknown disturbance into the control law and parameter adaptive law, respectively, the uncertainties of parameters and unknown external disturbance can be compensated. Simulation and hardware-in-the-loop tests are carried out on the SBW platform. Experiments show that the control strategy of the PMSM servo system designed in this article has good tracking accuracy and stability. 

Adaptive Control of PMSM Servo System for Steering-by-Wire System With Disturbances Observation

Ring-oscillator (RO)-based phase-locked loops (PLLs) are very attractive for system-on-chip applications for their compactness and tuning range, but suffer from high jitter and supply noise sensitivity. This paper presents a sub-sampling phase detector (SSPD)-based feedforward noise cancellation (FFNC) technique to improve these drawbacks of the RO PLL. The FFNC scheme utilizes the already available SSPD output to perform cancellation with high sensitivity while utilizing low power and area overhead. The 2- to 2.8-GHz RO PLL proof-of-principle prototype occupies 0.022 mm2 active area in 65 nm CMOS; it achieves a 633 fs rms jitter at 2.36 GHz with 5.86 mW power consumption and an figure of merit (FOMjitter) of −236.3 dB. The cancellation reduces the jitter by $1.4\times $ , the phase noise by 10.2 dB to −123.5 dBc/Hz at 300-kHz offset, and the RO supply sensitivity by 19.5 dB for a 1 mVpp 100-kHz noise tone on the RO supply.

A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector

A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.

Memory device including detection clock pattern generator for generating detection clock output signal including random data pattern

The present invention relates to a standby power saving switching mode power supply (SMPS) for reducing standby power consumed during dimming 0% control. According to the present invention, the standby power saving SMPS comprises: a main SMPS supplying power to an LED module when an object is detected from an object detection sensor so as to control the LED module to be a preset first brightness; and a micro SMPS integratedly formed with the main SMPS and, if the object is not detected from the object detection sensor or brightness of the LED module is 0%, supplying power to the LED module so as to always operate the LED module and supply standby power for operating the object detection sensor.

Yong-Hun Kim

Papers

Memory device including detection clock pattern generator for generating detection clock output signal including random data pattern

SMPSStandby power saving SMPS