This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverter-based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB.

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

In this article, a 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign–sign least-mean-squares (SSLMS) algorithm is applied to adaptation for not only a decision feedback equalizer (DFE) but also a continuous-time linear equalizer (CTLE) to unify the adaptation methods. This approach facilitates concurrent adaptation that results in short adaptation time and also reduces the extra hardware and power consumption. An average value of fourth- and fifth-post-cursors is used as an indicator for CTLE adaptation, and the validity is substantiated by numerical analysis and simulation. Furthermore, the concept of a biased data-level reference (dLev) is proposed and analyzed to alleviate insufficient adaptation of the SSLMS algorithm in the presence of pre-cursor inter-symbol interference (ISI). The proposed dLev is acquired by simply adjusting up and down ratios of the dLev update equation. The prototype test chip is implemented in 65-nm CMOS technology and occupies an active area of 0.174 mm2. The proposed adaptive equalizers compensate for the channel loss of up to 34 dB at 10.8 Gb/s. Total power consumption of the receiver is 37.2 mW at 10.8 Gb/s, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.1 pJ/b/dB is achieved.

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

Intelligent driving system requires more precise and reliable steering control, and steering-by-wire (SBW) technology can better adapt to the development of autonomous driving. The permanent magnet synchronous motor (PMSM) servo system is the actuator of the SBW. Aiming at the uncertainties of the PMSM servo system, a new adaptive control method for the PMSM servo system is proposed. Parameter adaptive laws are designed for each slowly varying parameter and unknown parameter, and robust terms are introduced to the adaptive laws for the parameter uncertainties. The convergence speed of the parameter adaptive law proposed can be improved by adjusting the parameters related to the convergence rate. To reduce the scope of disturbance uncertainties, the steering load disturbances are divided into a bounded unknown time-varying part and a predictable time-varying disturbance. Based on the Luenberger observer, the prediction term of the load torque is estimated by the current of PMSM in real time. By introducing boundary estimation and robust term of unknown disturbance into the control law and parameter adaptive law, respectively, the uncertainties of parameters and unknown external disturbance can be compensated. Simulation and hardware-in-the-loop tests are carried out on the SBW platform. Experiments show that the control strategy of the PMSM servo system designed in this article has good tracking accuracy and stability. 

Adaptive Control of PMSM Servo System for Steering-by-Wire System With Disturbances Observation

Ring-oscillator (RO)-based phase-locked loops (PLLs) are very attractive for system-on-chip applications for their compactness and tuning range, but suffer from high jitter and supply noise sensitivity. This paper presents a sub-sampling phase detector (SSPD)-based feedforward noise cancellation (FFNC) technique to improve these drawbacks of the RO PLL. The FFNC scheme utilizes the already available SSPD output to perform cancellation with high sensitivity while utilizing low power and area overhead. The 2- to 2.8-GHz RO PLL proof-of-principle prototype occupies 0.022 mm2 active area in 65 nm CMOS; it achieves a 633 fs rms jitter at 2.36 GHz with 5.86 mW power consumption and an figure of merit (FOMjitter) of −236.3 dB. The cancellation reduces the jitter by $1.4\times $ , the phase noise by 10.2 dB to −123.5 dBc/Hz at 300-kHz offset, and the RO supply sensitivity by 19.5 dB for a 1 mVpp 100-kHz noise tone on the RO supply.

A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector

This paper describes a 1-tap DFE with unfixed tap coefficient. According to the data patterns, the inter-symbol interference (ISI) is changed. The data patterns will be predicted using the DC level detector and the tap coefficient of the DFE will be adjusted to achieve high gain against high attenuation. The proposed 1-tap DFE with unfixed tap coefficient solves a high channel loss problem while it consumes low power. Designed in 65-nm CMOS technology, a 20 Gb/s receiver is composed of 1-tap half rate DFE with unfixed tap coefficient which compensates 20 dB attenuation, and it consumes 22.65 mW for 1-V supply.

A 20 Gbps 1-tap decision feedback equalizer with unfixed tap coefficient

In this brief, a 0.9-V 12-Gb/s quarter-rate two finite impulse response tap direct decision feedback equalizer (DFE) is presented. For a high-speed incorporated operation of both DFE summing and slicing, a common-mode-controlled charge-based latch (CMCCBL) is proposed. In a CMCCBL-based DFE, the common mode of the first tap feedback signal is changed to adjust the first tap feedback weight. Therefore, CMCCBL does not need the conventional first tap weighting transistors which increase the DFE feedback delay. The DFE core compensates for the FR4 printed circuit board channel loss of −22 dB at 6 GHz and consumes 4.16 mW achieving 0.347 pJ/bit for PRBS7 input. The active area of DFE is 0.0036 mm2 in a 65-nm CMOS process.

A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

This brief proposes a proportional-type angle filter with the variable feedback gain mechanism for motor drives using the encoder for angle feedback In this case, the angle measurement suffers from discontinuity that has to be made continuous through low-pass filters and observers There are three features The first designs a real-time feedback gain update rule to improve the closed-loop filtering performance by magnifying the feedback gain in transient periods The second introduces the disturbance observer (DOB) in the resultant proportional-type feedback filter for enhanced disturbance attenuation against the speed variations The third proves the useful properties of the filtering error convergence and performance recovery by investigating the filtering error dynamics A prototype 500-W permanent-magnet synchronous motor (PMSM) drive system validates the practical advantages of the proposed technique

Variable-Performance Proportional-Type Angle-Filtering System for Motor Drives

This paper presents a 2 GHz injection-locked PLL (ILPLL) with an injection-locked frequency divider (ILFD). Using a negative phase shift phenomenon of the ILFD, injection timing can be calibrated without a delay line. As a result, the proposed ILPLL achieves a simple background injection timing calibration for robustness of power supply variation. The test core has been fabricated in 65nm CMOS process consuming 3.74mW at 0.9V supply voltage.

An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider

An MMIC power amplifier using low-high doped GaAs MESFETs (LH-MESFETs) has been developed for a CDMA/AMPS dual mode cellular telephone. It is fully integrated on one chip (2.5/spl times/2.9 mm/sup 2/) including all matching circuits. For CDMA operation at frequency of 836.5 MHz, an efficiency of 25%, adjacent channel leakage power of -29 dBc at 885 kHz, and -48 dBc at 1980 kHz were obtained with an output power of 27.25 dBm and V/sub d/d=4.7 V. In AMPS operation, 30.5 dBm output power was obtained with 27.5 dB gain and 47% efficiency. The experimental results show that the gate periphery of LH-MESFETs and size of MMIC are much smaller than in previously reported similar amplifiers using conventional MESFET technology. This MMIC power amplifier is suitable for dual mode cellular applications.

Yong-Hun Kim

Papers

A 20 Gbps 1-tap decision feedback equalizer with unfixed tap coefficient

A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

Variable-Performance Proportional-Type Angle-Filtering System for Motor Drives

An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider

GaAs low-high doped MESFET MMIC power amplifier for CDMA/AMPS dual-mode cellular telephone