Yong-Hun Kim

TL;DR: This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a reference impedance (ZQ)-coded transmitter, and a phase-locked loop (PLL)-less clocking to overcome I/O speed limitation by the DRAM process.

TL;DR: This work exploits the half-bit previous input data with feed forward method and early/late signal from CDR to be tolerant to the input jitter and power noise.

TL;DR: A novel integrated time register and arithmetic circuit (TRAC) for time-domain signal processing (TDSP) with post-layout data simulated in 110nm CMOS technology is described.

TL;DR: The proposed scheme enables computation of optimal current reference for a torque reference under all operating regions, including the maximum torque per ampere (MTPA), flux weakening (FW), maximum current (MC), andmaximum torque per voltage (MTPV), using numerical optimization techniques to simplify the problems and obtain the corresponding solutions with reduced computation burden.

TL;DR: A 1/4th baud-rate continuous-time linear equalizer (CTLE) and a two-tap DFE, which compensates 21.7-dB channel loss and operates with 11.5-Gb/s data rate as it consumes 25.35 mW from 1.3 V supply in a 110-nm CMOS technology.