This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverter-based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB.

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

In this article, a 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign–sign least-mean-squares (SSLMS) algorithm is applied to adaptation for not only a decision feedback equalizer (DFE) but also a continuous-time linear equalizer (CTLE) to unify the adaptation methods. This approach facilitates concurrent adaptation that results in short adaptation time and also reduces the extra hardware and power consumption. An average value of fourth- and fifth-post-cursors is used as an indicator for CTLE adaptation, and the validity is substantiated by numerical analysis and simulation. Furthermore, the concept of a biased data-level reference (dLev) is proposed and analyzed to alleviate insufficient adaptation of the SSLMS algorithm in the presence of pre-cursor inter-symbol interference (ISI). The proposed dLev is acquired by simply adjusting up and down ratios of the dLev update equation. The prototype test chip is implemented in 65-nm CMOS technology and occupies an active area of 0.174 mm2. The proposed adaptive equalizers compensate for the channel loss of up to 34 dB at 10.8 Gb/s. Total power consumption of the receiver is 37.2 mW at 10.8 Gb/s, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.1 pJ/b/dB is achieved.

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

Intelligent driving system requires more precise and reliable steering control, and steering-by-wire (SBW) technology can better adapt to the development of autonomous driving. The permanent magnet synchronous motor (PMSM) servo system is the actuator of the SBW. Aiming at the uncertainties of the PMSM servo system, a new adaptive control method for the PMSM servo system is proposed. Parameter adaptive laws are designed for each slowly varying parameter and unknown parameter, and robust terms are introduced to the adaptive laws for the parameter uncertainties. The convergence speed of the parameter adaptive law proposed can be improved by adjusting the parameters related to the convergence rate. To reduce the scope of disturbance uncertainties, the steering load disturbances are divided into a bounded unknown time-varying part and a predictable time-varying disturbance. Based on the Luenberger observer, the prediction term of the load torque is estimated by the current of PMSM in real time. By introducing boundary estimation and robust term of unknown disturbance into the control law and parameter adaptive law, respectively, the uncertainties of parameters and unknown external disturbance can be compensated. Simulation and hardware-in-the-loop tests are carried out on the SBW platform. Experiments show that the control strategy of the PMSM servo system designed in this article has good tracking accuracy and stability. 

Adaptive Control of PMSM Servo System for Steering-by-Wire System With Disturbances Observation

Ring-oscillator (RO)-based phase-locked loops (PLLs) are very attractive for system-on-chip applications for their compactness and tuning range, but suffer from high jitter and supply noise sensitivity. This paper presents a sub-sampling phase detector (SSPD)-based feedforward noise cancellation (FFNC) technique to improve these drawbacks of the RO PLL. The FFNC scheme utilizes the already available SSPD output to perform cancellation with high sensitivity while utilizing low power and area overhead. The 2- to 2.8-GHz RO PLL proof-of-principle prototype occupies 0.022 mm2 active area in 65 nm CMOS; it achieves a 633 fs rms jitter at 2.36 GHz with 5.86 mW power consumption and an figure of merit (FOMjitter) of −236.3 dB. The cancellation reduces the jitter by $1.4\times $ , the phase noise by 10.2 dB to −123.5 dBc/Hz at 300-kHz offset, and the RO supply sensitivity by 19.5 dB for a 1 mVpp 100-kHz noise tone on the RO supply.

A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector

This brief presents a reference-less baud-rate digital clock and data recovery (CDR) with a data decision feedback (DDF) with a direct feedback method (DFM). The DDF with DFM has been used for the equalization of the channel loss for the serial link with a decision feedback equalizer. However, we apply DDF with DFM to the baud-rate CDR to reduce the number of data samplers, which is dropped to 2/3 compared to conventional baud-rate CDR. As a result, the power consumption and mismatch problem of the data samplers can be reduced. The test chip fabricated in 65-nm CMOS technology operates at a 10-Gb/s data rate with 13.84-mW power consumption.

A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method

This study suggests a non-linear output voltage tracking controller for DC/DC boost converters in the form of a classical cascade control structure. Non-linearities in the converter dynamics as well as parameter uncertainties and load variations are considered. The first contribution of this study is the design of an auto-tuner, which automatically adjusts the control gain according to the output voltage error to enhance transient performance. The second contribution involves proving that the closed-loop system ensures the performance recovery without any steady-state errors in the presence of parameter and load variations. The effectiveness of the proposed algorithm was verified through experimental investigations using a 5 kW prototype DC/DC boost converter.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2018.6021

Output voltage tracking controller embedding auto-tuning algorithm for DC/DC boost converters

Primary mediastinal leiomyosarcoma is an extremely rare neoplasm that arises from smooth muscle, usually in the esophagus or main vessels, but rarely from small vessels in the soft tissues of the mediastinum. The clinical findings depend mostly on its size and the subsequent compression of neighboring structures. The treatment of choice is surgical removal. We report the case of a 78-year-old female who presented with esophageal compression symptoms due to a 9-cm inhomogeneous mass in the posterior mediastinum. A computed tomography (CT)-guided gun biopsy and immunohistochemistry established the pathological diagnosis of leiomyosarcoma with a high grade of malignancy. Surgery was performed because of local invasion involving the aorta and diaphragm. The literature is reviewed and the pathology discussed.

A case of leiomyosarcoma arising from the posterior mediastinum

Abstract Background Umbilical discharge in an adult is rare and generates broad diagnostic considerations. Umbilical anatomy is variable owing to congenital abnormalities and acquired pathology such as umbilical hernias. The umbilicus can be a site of primary or metastatic malignancy or endometriosis. Case presentation A 40-year-old white American woman came to the clinic with a 2-day history of spontaneous umbilical bleeding. She reported periumbilical pain associated with nausea and emesis. There were no visible skin abnormalities, but deep palpation of the abdomen produced a thin, watery, serosanguineous fluid from the umbilicus. She experienced a similar episode of umbilical bleeding 5 years prior without clear cause. Laboratory workup was notable for mildly elevated C-reactive protein . Computed tomography imaging revealed a fat-containing umbilical hernia with fat necrosis, necessitating complete surgical resection of the umbilicus. Conclusions Umbilical hernia with fat necrosis is a rare condition that should be considered in adults with umbilical discharge. Additional diagnostic considerations in adults with spontaneous umbilical bleeding/discharge include embryonal remnants, omphalitis, and metastasis. If the cause is not readily apparent on physical exam, imaging with computed tomography should be considered to assess for hernia and embryonal anomalies. 

/pdf/a-woman-with-recurrent-umbilical-bleeding-a-case-report-3d7mfx27.pdf

A woman with recurrent umbilical bleeding: a case report

This Letter proposes a novel technique for automatic position offset calibration for permanent-magnet synchronous machine (PMSM) drives. Contrary to existing methods, the proposed technique estimates and compensates for the position offset without using machine true parameters or signal injection, which is possible under the condition of zero-current control at high enough speed where parameter-dependent terms are eliminated. To achieve this condition using uncertain parameters, speed control with absolute value feedback and model-free current control are devised. Additionally, under this condition, not only the misalignment of the position sensor but also the sensor delay can be considered as the position offset, which improves the accuracy of the calibration. The proposed approach will be verified by experimental results.

Yong-Hun Kim

Papers

A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method

Output voltage tracking controller embedding auto-tuning algorithm for DC/DC boost converters

A case of leiomyosarcoma arising from the posterior mediastinum

A woman with recurrent umbilical bleeding: a case report

Auto-calibration of position offset for PMSM drives with uncertain parameters