A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

Tunable sector buffer for wide bandwidth resonant global clock distribution

A tunable inductor arrangement arrangable on a chip or substrate is disclosed. The tunable inductor comprises a first winding part connected at one end to a first input of the tunable inductor arrangement, a second winding part connected at one end to the other end of the first winding part, a third winding part connected at one end to a second input of the tunable inductor arrangement, a fourth winding part connected at one end to the other end of the third winding part, and a switch arrangement arranged to tune the tunable inductor arrangement by selectively provide a circuit either comprising the first and fourth winding parts in parallel and the second and third winding parts in parallel, with the parallel couplings in series between the first and second inputs, or a circuit comprising the first, second, fourth and third winding parts in series between the first and second inputs. A transceiver, communication device, method and computer program are also disclosed.

Tunable inductor arrangement, transceiver, method and computer program

A tunable inductor arrangement arrangable on a chip or substrate is disclosed. The tunable inductor comprises a first winding part connected at one end to a first input of the tunable inductor arrangement, a second winding part connected at one end to the other end of the first winding part, a third winding part connected at one end to a second input of the tunable inductor arrangement, a fourth winding part connected at one end to the other end of the third winding part, and a switch arrangement arranged to tune the tunable inductor arrangement. Tuning is performed by selectively provide any of a circuit comprising the first and third winding parts in series between the first and second inputs, or a circuit comprising the first, second, fourth and third winding parts in series between the first and second inputs. The first and third winding parts are arranged on the chip or substrate such that magnetic fields of the first and third windings are essentially common, and the second and fourth winding parts are arranged to cancel electro-magnetic coupling with the first and third winding parts. A receiver, transceiver, communication device, method and computer program are also disclosed.

A processing system for a capacitive sensing input device comprises a charge integrator, a circuit element having a first resistance, and a first switch coupled with the circuit element. The first circuit element is disposed in series with an input of the charge integrator. The first switch is configured to alter the first resistance to a second resistance when selectively closed during at least a portion of an integration phase of the charge integrator. The second resistance is lower than the first resistance.

Variable time anti-aliasing filter

A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.

Clock buffers with pulse drive capability for power efficiency

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, at least one inductor, at least one tunable resistance switch, and a capacitor network. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Variable resistance switch for wide bandwidth resonant global clock distribution

A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Yong I. Kim

Papers

Tunable sector buffer for wide bandwidth resonant global clock distribution

Variable resistance switch for wide bandwidth resonant global clock distribution

Wide bandwidth resonant global clock distribution