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William Robert Reohr

Researcher at IBM

Publications -  62
Citations -  2304

William Robert Reohr is an academic researcher from IBM. The author has contributed to research in topics: Sense amplifier & Dram. The author has an hindex of 27, co-authored 62 publications receiving 2287 citations.

Papers
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Proceedings ArticleDOI

A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell

TL;DR: The magnetic tunnel junction (MTJ) MRAM is dramatically different and achieves four orders of magnitude better bandwidth to sense power ratio by utilizing a high resistance and high magneto-resistance (MR) MTJ and including a FET switch in each cell.
Patent

Method and apparatus for automated migration of data among storage centers

TL;DR: In this paper, a method for controlling the storage of data among multiple regional storage centers coupled through a network in a global storage system is provided, which includes steps of: defining at least one dataset comprising at least a subset of the data stored in the global storage systems; defining a ruleset for determining where to store the dataset; obtaining information regarding a demand for the dataset through one or more data requesting entities operating in the globally storage system; and determining, as a function of the ruleset, information regarding the location for storing the dataset among regional storage centres having available resources that
Patent

Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories

TL;DR: In this article, a memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation.
Journal ArticleDOI

Memories of tomorrow

TL;DR: With the promise of nonvolatility, practically infinite write endurance, and short read and write times, magnetic tunnel junction magnetic random access memory could become a future mainstream memory technology as mentioned in this paper.
Patent

Dynamic memory architecture employing passive expiration of data

TL;DR: In this paper, a time stamp memory and a timer are coupled to a control circuitry for passively tracking expired data in a dynamic memory, where the control circuitry is operative to manage the information stored in the memory relating to the refresh status of one or more corresponding data entries in the dynamic memory.