Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors. Error detection is based on flagging spurious transitions in the state-holding latch node. The RazorII flip-flop naturally detects logic and register SER. We implement a 64-bit processor in 0.13 mum technology which uses RazorII for SER tolerance and dynamic supply adaptation. RazorII based DVS allows elimination of safety margins and operation at the point of first failure of the processor. We tested and measured 32 different dies and obtained 33% energy savings over traditional DVS using RazorII for supply voltage control. We demonstrate SER tolerance on the RazorII processor through radiation experiments.

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

We take advantage of these findings and propose a Razor II approach that introduces two components. First, instead of performing both error detection and correction in the FF, Razor II performs only detection in the FF, while correction is performed through architectural replay.

Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance

A home entertainment system for video games and other applications includes a main unit and handheld controllers. The handheld controllers sense their own motion by detecting illumination emitted by emitters positioned at either side of a display. The controllers can be plugged into expansion units that customize the overall control interface for particular applications including but not limited to legacy video games.

Video game system with wireless modular handheld controller

An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

A game operating device (controller) includes a longitudinal housing, and a holding portion held by hand to be wrapped by its palm it is formed in the housing. A direction switch is provided on an upper surface at a position where it can be operated by thumb of the hand holding the holding portion, and a start switch and a select switch are provided backward thereof. An X button 46 and a Y button are further arranged in line on the upper surface of the housing. An imaging information arithmetic unit is provided at a front end of the housing in a longitudinal direction in such a manner that an imaging device thereof is exposed from a front-end surface. A concave portion is formed on a lower surface at a position corresponding to the direction switch. The concave portion includes a valley and two inclined surfaces. An A button capable of being operated by index finger of the hand holding the holding portion is provided on the backward inclined surface. By processing an image signal obtained by imaging an infrared ray from LED modules by the imaging device, it is possible to obtain an operation signal varying according to a position and/or attitude of the controller.

Game operating device

A distributed critical-path timing monitor (CPM) is designed as part of the POWER6trade microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process variation, localized noise and VDD droop, or clock stability. It tracks critical-path delay to within 3 FO2 delays at extreme operating voltages with a standard deviation less than frac12 an FO2 delay. The CPM detects DC VDD droops greater than 10mV and tracks timing changes greater than 1 FO2 delay.

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

Microprocessor voltage levels include substantial margin to deal with process variation, system power supply variation, workload induced thermal and voltage variation, aging, random uncertainty, and test inaccuracy. This margin allows the microprocessor to operate correctly during worst-case conditions, but during typical conditions it is larger than necessary and wastes energy. We present a mechanism that reduces excess voltage margin by (1) introducing a critical path monitor (CPM) circuit that measures available timing margin in real-time, (2) coupling the CPM output to the clock generation circuit to adjust clock frequency within cycles in response to excess or inadequate timing margin, and (3) adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target. We implemented this mechanism in a prototype IBM POWER7 server. During better-than-worst case conditions our guardband management mechanism reduces the average voltage setting 137-152 mV below nominal, resulting in average processor power reduction of 24% with no performance loss while running industry-standard benchmarks.

https://researcher.watson.ibm.com/researcher/files/us-lefurgy/micro44_Charles_Lefurgy_slides.pdf

Active management of timing guardband to save energy in POWER7

A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies. Theory predicts that the data passing though the clocked logic will change the clock frequency by less than 1.25%. A resonant clock test chip was designed and fabricated in an IBM 0.13-/spl mu/m partially depleted SOI process. Although the test chip was designed to operate in the gigahertz range using integrated inductors, startup difficulties required the addition of external inductance to reduce the resonant frequency so that the effects of the parasitic capacitance could be measured. The parasitic capacitance is approximately 40 pF per clock phase, resulting in a clock frequency between 106 and 146 MHz, depending on biasing. At its most efficient bias point, the clock dissipated 2.09 mW, which is approximately 35% less power than a conventional, buffer-driven clock. The maximum period jitter measured in the resonant clock due to changing data in the clocked latches was 55 ps at 124 MHz, or 0.68% of the clock period.

Resonant clocking using distributed parasitic capacitance

Power7 implements several new adaptive power management techniques which, in concert with the EnergyScale firmware, let it proactively exploit variations in workload, environmental conditions, and overall system use to meet customer-directed power and performance goals. These innovative features include per-core frequency scaling with available autonomic frequency control, per-chip automated voltage slewing, power consumption estimation, and hardware instrumentation assist.

Introducing the Adaptive Energy Management Features of the Power7 Chip

Microprocessor voltage levels traditionally include substantial margin to ensure reliable operation despite variations in manufacturing, workload, and environmental parameters This margin allows the microprocessor to function correctly during worst-case conditions, but during typical operation it is larger than necessary and wastes energy The authors present a mechanism that reduces excess voltage margin by introducing a critical-path monitor (CPM) circuit that measures available timing margin in real time; coupling the CPM output to the clock generation circuit to rapidly adjust clock frequency in response to excess or inadequate timing margin; and adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target They first demonstrated this mechanism in an IBM Power7 server and proved its effectiveness in the Power7+ product Power consumption on the VDD rail was reduced by 11 percent for SPEC CPU2006 workloads with negligible performance loss yet increased protection against noise events

https://researcher.watson.ibm.com/researcher/files/us-lefurgy/MICROmag2013_Lefurgy_final.pdf

Alan J. Drake

Papers

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

Active management of timing guardband to save energy in POWER7

Resonant clocking using distributed parasitic capacitance

Introducing the Adaptive Energy Management Features of the Power7 Chip

Active Guardband Management in Power7+ to Save Energy and Maintain Reliability