The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

New and improved dielectric materials with high dielectric breakdown strength are required for both high energy density electric energy storage applications and continued miniaturization of electronic devices. Despite much practical significance, accurate ab initio predictions of dielectric breakdown strength for complex materials are beyond the current state-of-the art. Here we take an alternative data-enabled route to address this design problem. Our informatics-based approach employs a transferable machine learning model, trained and validated on a limited amount of accurate data generated through laborious first-principles computations, to predict intrinsic dielectric breakdown strength of several hundreds of chemical compositions in a highly efficient manner. While the adopted approach is quite general, here we take up a specific example of perovskite materials to demonstrate the efficacy of our method. Starting from several thousands of compounds, we systematically downselect 209 insultors which are...

Machine Learning Assisted Predictions of Intrinsic Dielectric Breakdown Strength of ABX3 Perovskites

Modern microelectronic device manufacture requires single-crystal silicon substrates of unprecedented uniformity and purity, As the device feature lengths shrink into the realm of the nanoscale, it is becoming unlikely that the traditional technique of empirical process design and optimization in both crystal growth and wafer processing will suffice for meeting the dynamically evolving specifications. These circumstances are creating more demand for a derailed understanding of the physical mechanisms that dictate the evolution of crystalline silicon microstructure and associated electronic properties. This article describes modeling efforts based on the dynamics of native point defects in silicon during crystal growth, which are aimed at developing comprehensive and robust tools for predicting microdefect distribution as a function of operating conditions. These tools are not developed independently of experimental characterization but rather are designed to take advantage of the very detailed information database available for silicon generated by decades of industrial attention. The bulk of the article is focused on two specific microdefect structures observed in Czochralski crystalline silicon, the oxidation-induced stacking fault ring (OSF-ring) and octahedral voids; the latter is a current limitation on the quality of commercial CZ silicon crystals and the subject of intense research. (C) 2000 Published by Elsevier Science S.A.

Defect engineering of Czochralski single-crystal silicon

Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale. The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that Pb concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen. Finally, the roles of contamination, particles, metals, hydrocarbons etc. are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above.

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Oxidation of silicon: the VLSI gate dielectric

TECHNOLOGIES AND DEVICES History of Low-Power Electronics (Christian Piguet, CSEM&LAP-EPFL, Switzerland) Evolution of Deep Submicron Bulk and SOI Technologies (Marc Belleville, Olivier Faynot, CEA-LETI, Grenoble, France) Leakage in CMOS Nanometric Technologies (Antoni Ferre, Joan Figueras, UPC, Barcelona, Spain) Microelectronics, Nanoelectronics and the Future of Electronics" (Jing Wang, Mark Lundstrom, Purdue University, West Lafayette) Advanced Research in On-Chip Optical Interconnects (Ian O'Connor, Frederic Gaffiot, Ecole Centrale de Lyon, Lyon, France) LOW-POWER CIRCUITS Modeling for Designing in Deep Submicron Technologies (Daniel Auvergne, Philippe Maurine, Nadine Azemard, LIRMM, Montpellier, France) Logic Circuits and Standard Cells (Christian Piguet, CSEM&LAP-EPFL, Switzerland) Low-Power Very Fast Dynamic Logic Circuits (Jiren Yuan, Lund University, Sweden) Low-Power Arithmetic Operators (Arnaud Tisserand, INRIA, Lyon, France) Circuit Techniques for Dynamic Power Reduction (Dimitrios Soudris, Democritus University of Thrace, Greece) VHDL for Low-Power (Amara Amara, ISEP, Paris, France and Philippe Royannez, Texas Instruments, France) Clocking Multi-GHz Systems (Vojin G. Oklobdzija, Davis University, CA) Circuit Techniques for Leakage Reduction (Amit Agarwal, Chris H. Kim, Kaushik Roy, Purdue University) Low-Power and Low-Voltage Communication for SoCs (Christer Svensson, Linkoeping University, Sweden) Adiabatic and Clock-Powered Circuits (Lars Svensson, Chalmers University, Sweden) Weak Inversion for Ultimate Low-Power Logic (Eric A. Vittoz, CSEM, Switzerland) Robustness of Digital Circuits at Lower Voltages (Harry Veendrick, Philips, Netherlands) CAD TOOLS FOR LOW-POWER High Level Power Estimation and Analysis (Wolfgang Nebel, Oldenburg University, Germany, Domenik Helms, OFFIS, Germany) Power Macro-Models for High-Level Power Estimation (Enrico Macii, Politecnico di Torino, Italy, Massimo Poncino, Universita di Verona, Italy) Synopsys Low-Power Design Flow (Renu Mehra, Barry Pangrle, Synopsys Inc.) Magma Low Power Flow (Ed Huijbregts, Lars Kruse, Eric Seelen, Magma Design Automation Inc.) Sequence Design Flow for Low-Power Design (Jerry Frenkil, Sequence Design)

Low-Power CMOS Circuits: Technology, Logic Design and CAD Tools

An analytical method to separate the diffusion and generation components of pn junction leakage currents is developed The voltage dependence between reverse current and capacitance in pn junctions is measured, and an approximately linear relationship between current density (J) and depletion width (W) is derived In this relationship, the diffusion component corresponds to linearly extrapolated value of J at W=0, and the generation component corresponds to the rate at which J increases with W as voltage is applied This method allows both components of the leakage current to be obtained for Czochralski, epitaxial, and intrinsic gettering wafers Separated diffusion components strongly depend on silicon wafers mainly due to the change of minority carrier density and the diffusion of minority carriers On the other hand, the generation component increases with increases in the electric field applied to the junction for all wafers We found that this electric field effect on the generation component can be 

Separation and analysis of diffusion and generation components of pn junction leakage current in various silicon wafers

We used heat treatment to intentionally introduce various structural defects in Czochralski silicon substrates. The type, size, and number density of the induced defects were surveyed with transmission electron microscopy, and the defects were then incorporated into SiO2 films (10–50 nm thick) during thermal oxidation in dry O2. The effect of the defects on dielectric strength of the SiO2 films was examined with a time zero dielectric breakdown method. Larger platelet oxygen precipitates caused greater decreases of the breakdown field, and precipitates smaller than the SiO2 film thickness did not appreciably reduce the breakdown field. Every large platelet oxygen precipitate incorporated in the SiO2 film caused a degradation. Octahedral oxygen precipitates caused little degradation. The breakdown field was higher than 7 MV/cm and did not depend much on the SiO2 film thickness and precipitate size. We discussed possible mechanisms for the degradation due to both kinds of precipitates. Oxidation‐induced sta...

Degradation of dielectric breakdown field of thermal SiO2 films due to structural defects in Czochralski silicon substrates

The reverse-bias leakage characteristics of silicon pn junctions have been investigated with particular attention to the effects of various types of oxygen-related defects, such as oxygen precipitates, oxidation induced stacking fault, and grown-in defects. The effects of oxygen-related defects on the leakage current of pn junctions in intrinsic gettering wafers and precipitation annealed wafers have been investigated quantitatively, and the field oxidation temperature used to form pn junctions has been found to be an important factor in determining the pn junction leakage current because oxygen-related defects are formed during low temperature field oxidation. It has also been found that grown-in oxidation induced stacking faults degrade the leakage characteristics. Grown-in defects that are well known to degrade the oxide breakdown characteristics were found to have some effects on the increase of the leakage current. In addition, it is recognized that the leakage current of pn junctions formed in wafer...

Effects of oxygen-related defects on the leakage current of silicon p/n junctions

This study investigated the dielectric breakdown characteristics of thermal oxide films grown by dry and wet oxidation. Oxide films grown by wet oxidation have lower B‐mode failure rates and higher B‐mode breakdown fields. On the other hand, the reliability of C mode of oxide films does not differ consistently between films grown by dry and wet oxidation. These results indicate that as‐grown defect causing B‐mode failure may shrink or be reduced during wet oxidation.

Effect of oxidation ambient on the dielectric breakdown characteristics of thermal oxide films of silicon

We examine the effect of bulk microdefects (BMD) intentionally introduced in Czochralski silicon substrates by heat treatment on the dielectric breakdown of thermally grown SiO2 films. Transmission electron microscope observations reveal that the BMD consist of oxygen precipitates, perfect dislocation loops, and faulted dislocation loops. When the BMD are incorporated into the SiO2 film during thermal oxidation, an apparent decrease in the breakdown field is observed. The size of the oxygen precipitates has a clear relationship with the breakdown field: larger oxygen precipitate causes greater degradation. The dislocation loops are unrelated to the breakdown field.

Yoshio Murakami

Papers

Separation and analysis of diffusion and generation components of pn junction leakage current in various silicon wafers

Degradation of dielectric breakdown field of thermal SiO2 films due to structural defects in Czochralski silicon substrates

Effects of oxygen-related defects on the leakage current of silicon p/n junctions

Effect of oxidation ambient on the dielectric breakdown characteristics of thermal oxide films of silicon

Effect of bulk microdefects induced in heat‐treated Czochralski silicon on dielectric breakdown of thermal SiO2 films