In this article, we review the recent progress of ferroelectric field-effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2), ten years after the first report on such a device. With a focus on the use of FeFET for nonvolatile memory application, we discuss its basic operation principles, switching mechanisms, device types, material properties and array structures. Key device performance metrics such as cycling endurance, retention, memory window, multi-level operation and scaling capability are analyzed. We also briefly survey recent developments in alternative applications for FeFETs including neuromorphic and in-memory computing as well as radiofrequency devices.

Ferroelectric field-effect transistors based on HfO2: a review.

We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

An optimization principle for ferroelectric FET (FeFET), centered around charge matching between the ferroelectric and its underlying semiconductor, is theoretically investigated. This letter shows that, by properly reducing the ferroelectric polarization charge and its background dielectric constant, charge matching can be improved to enable simultaneously: i) reduction of the interlayer and semiconductor electric fields during programming, reading, and retention, leading to prolonged endurance and retention; ii) improvement of the memory window; and iii) suppression of device-to-device variations by affording full polarization switching. These attributes provide an incentive for the presentation of the proposed guidelines for FeFET optimization as detailed in this letter.

Guidelines for Ferroelectric FET Reliability Optimization: Charge Matching

In this work, a comprehensive study of random spatial fluctuation of the ferroelectric (FE) phase and dielectric (DE) phase in FeFETs is conducted to understand its impact on device variation. It is found that: i) there exists a certain DE percentage threshold that below which the increase of the DE phase does not significantly impact the device memory window and variation and only above which evident device degradation can be observed; ii) increasing the DE phase increases the variation in the memory window and the coercive field distribution further exacerbates the variation, hence degrading the sensing margin; iii) decreasing the number of grains degrades the device variation, which calls for further grain size engineering for variation suppression.

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET

Neuro-inspired deep learning algorithm has shown promising futures for artificial intelligence (AI). Despite the remarkable progress on software-based neural network, the traditional von-Neumann hardware architecture has suffered from limited energy efficiency while facing unprecedented large amount of data. In order to meet the performance requirement of neuro-inspired computing, the large-scale vector-matrix multiplication is preferred to be performed in-situ, namely compute-in-memory (CIM). Non-volatile memory devices with different materials have been proposed for weight storage as synaptic devices. Among them, the HfO2-based ferroelectric devices have obtained great attention because of their low energy consumption, good CMOS compatibility and multi-bit per cell potential. In this review, recent trends and prospects of the ferroelectric synaptic devices are surveyed. First, we present the three-terminal synaptic devices based on ferroelectric field effect transistor (FeFET), and discuss the switching physics of the intermediate states, the back-end-of-line (BEOL) integration and the 3D NAND architecture design. Then, we introduce hybrid precision synapse concept that leverages the volatile charges on the gate capacitor of FeFET and the non-volatile polarization on the gate dielectric of FeFET. Lastly, we review two-terminal synaptic devices using ferroelectric tunnel junction (FTJ) and ferroelectric capacitor (FeCAP). Design margins of the crossbar array with FTJ and FeCAP are analyzed.

Ferroelectric HfO2-based synaptic devices: recent trends and prospects

This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.

Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution

This article investigates the impact of interface trapped-charge variations on the dimensional scaling of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) under two scenarios: a uniform ferroelectric and random ferroelectric-dielectric (FE-DE) phase distribution. Our study indicates that both memory window (MW) and read margin decrease with increasing trap density ( ${ }$ ), and the MW of FeFET devices with scaled channel width can be more vulnerable to the trapped-charge variations than that with scaled gate length. Under the presence of the FE-DE phase variation, for low ${ }$ , the impact of trapped charges is mainly on the MW degradation for the high MW instances. As the ${ }$ continues to rise, the trapped charges can further worsen the worst case MW significantly. Besides, when down-scaling the interfacial layer thickness of the FeFET device to increase the MW, the increased $ \sigma $ MW due to the random interface trapped charges may also need to be considered. Our study may provide insights for device design with advanced FeFET NVMs.

Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories

Trapping-detrapping of a single electron via an individual trap in metal-oxide–semiconductor field-effect transistor (MOSFET) gate dielectric constitutes two-level random telegraph signals. Recent 3-D technology computer-aided design (TCAD) simulations, on an individual MOSFET, revealed that with the position of the trap as a random variable, resulting random telegraph signals relative magnitude $\Delta I_{{\boldsymbol {{d}}}}/I_{{\boldsymbol {{d}}}}$ in the subthreshold current at low drain voltage can have two distinct distributions: a headed one for a percolation-free channel and a tail one for a percolative channel. The latter may be effectively treated by a literature formula: ( $\Delta I_{{\boldsymbol {{d}}}}/I_{{\boldsymbol {{d}}}})=(I_{\mathbf {loc}}/I_{{\boldsymbol {{d}}}})^{\mathrm {\mathbf {2}}}$ , where $I_{\mathbf {loc}}$ is the local current around the trap. In this paper, we show how to make this formula practically useful. First, we conduct 3-D TCAD simulations on a $35\times 35$ -nm $^{\mathrm {\mathbf {2}}}$ channel to provide $\Delta I_{{\boldsymbol {{d}}}}/I_{{\boldsymbol {{d}}}}$ for a few positions of the trap. This leads to a new statistical model in closed form, which can reproduce headed distributions. Straightforwardly, key criteria are drawn from the model, which can act as guidelines for the adequate use of the $I_{\mathbf {loc}}/I_{{\boldsymbol {{d}}}}$ formula. Extension to threshold voltage shift counterparts, from subthreshold through transition to inversion, is successfully achieved. Importantly, use of the model may overcome the drawbacks of the statistical experiment or simulation in the field.

https://ir.nctu.edu.tw:443/bitstream/11536/24625/1/000338027200039.pdf

A Statistical Model for the Headed and Tail Distributions of Random Telegraph Signal Magnitudes in Nanoscale MOSFETs

This brief investigates scaled 2-D MoS2 ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) considering the trapped-charge-induced variability with the aid of Technology Computer Aided Design (TCAD) atomistic simulations. Our study indicates that, compared with the Si channel, the monolayer MoS2 channel with larger electron affinity and bandgap energy can result in an FeFET NVM with larger memory window (MW). Moreover, due to its lower channel permittivity and channel thickness, the 2-D MoS2 FeFET possesses a superior immunity to trapped-charge-induced variability, and the gap in MW between MoS2 and Si FeFETs enlarges under the presence of trapped charges. Besides, due to its atomically thin channel thickness and superior electrostatic integrity, the scaled 2-D MoS2 FeFET possesses a remarkably better read margin than the Si counterpart. Our study may provide insights for future scaling of FeFET NVMs.

Comparison of 2-D MoS2 and Si Ferroelectric FET Nonvolatile Memories Considering the Trapped-Charge-Induced Variability

This work investigates the interfacial-layer (IL) surface roughness induced random variation in scaled 2D FeFET NVMs with the aid of TCAD atomistic simulations. Our study indicates that the IL surface roughness variation may significantly impact the FeFET NVM, and the variability in memory window (MW) increases as the gate length is scaled down. We have also compared the IL surface roughness induced variation for 2D FeFETs and Si FeFETs. Besides, we have demonstrated that using high-k spacer design can mitigate the IL surface roughness induced variation in addition to raising the MW. The impact of high-k spacers increases with the downscaling of gate length.

You-Sheng Liu

Papers

Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution

Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories

A Statistical Model for the Headed and Tail Distributions of Random Telegraph Signal Magnitudes in Nanoscale MOSFETs

Comparison of 2-D MoS2 and Si Ferroelectric FET Nonvolatile Memories Considering the Trapped-Charge-Induced Variability

Investigation of Interlayer Surface Roughness induced Variation in Scaled 2D Ferroelectric-FET Nonvolatile Memories