The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.

Device and technology evolution for Si-based RF integrated circuits

A bias circuit operable to supply a bias current to a first transistor includes: a second transistor having a collector terminal connected to a first power supply; a first resistance element having one end connected to an emitter terminal of the second transistor and having the other end connected to a base terminal of the first transistor; a second resistance element having one end connected to the emitter terminal of the second transistor and having the other end connected to ground potential; at least one third resistance element provided between a base terminal of the second transistor and a second power supply; and a plurality of temperature compensation circuits connected to the base terminal of the second transistor which are operable to control a base potential of the second transistor so that the potential falls as a temperature rises.

Radio frequency power amplifier

An RFID reader accessible thorough a personal computer and includes a PC card interface and a controller both operating according to clock signals from a crystal oscillator. The RFID reader further includes a linearized power amplifier modulator in a transmit path, a receive chain capable of demodulating EPCglobal Class_1 and Class_0 signals from RFID tags, and an integrated switching device for selecting one of a plurality of antenna for transmitting or receiving RF signals.

Multiprotocol RFID reader

This paper presents a highly linear differential cascode CMOS power amplifier (PA) with gate bias circuits in Common Source (CS) and Common Gate (CG) amplifiers. The proposed Class-D bias circuit at the gate of a CS amplifier injects a reshaped envelope signal only when the envelope signal is above a certain threshold voltage. This improves the linearity of the PA without significantly degrading the efficiency in a high-power region. In addition, the proposed bias circuit at the gate of a CG amplifier controls the second-order nonlinear components to improve the linearity and to reduce the sideband (IMD or ACLR) asymmetry, simultaneously. A single-stage PA including the bias circuits was fabricated using a 0.18-μ m CMOS process, with an integrated passive device (IPD) transmission line transformer (TLT). With a 3.5 V supply, the measurements show that 26.8 dBm with 43.3% PAE at -37 dBc ACLR (5 MHz offset) and 27.8 dBm with 45.8% PAE at -33 dBc ACLR (5 MHz offset) at 1.85 GHz under 3GPP WCDMA test without digital pre-distortions.

Integrated Bias Circuits of RF CMOS Cascode Power Amplifier for Linearity Enhancement

Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique

A personal communications service/wide-band code division multiple access (PCS/W-CDMA) dual-band monolithic microwave integrated circuit (MMIC) power amplifier with a single-chip MMIC and a single-path output matching network is demonstrated by adopting a newly proposed on-chip linearizer. The linearizer is composed of the base-emitter diode of an active bias transistor and a capacitor to provide an RF short at the base node of the active bias transistor. The linearizer enhances the linearity of the power amplifier effectively for both PCS and W-CDMA bands with no additional DC power consumption, and has negligible insertion power loss with almost no increase in die area. It improves the input 1-dB gain compression point by 18.5 (20) dB and phase distortion by 6.1/spl deg/ (12.42/spl deg/) at an output power of 28 (28) dBm for the PCS (W-CDMA) band while keeping the base bias voltage of the power amplifier as designed. A PCS and W-CDMA dual-band InGaP heterojunction bipolar transistor MMIC power amplifier with single input and output and no switch for band selection is embodied by implementing the linearizer and by designing the amplifier to have broad-band characteristics. The dual-band power amplifier exhibits an output power of 30 (28.5) dBm, power-added efficiency of 39.5 % (36 %), and adjacent channel power ratio of -46 (-50) dBc at the output power of 28 (28) dBm under 3.4-V operation voltage for PCS (W-CDMA) applications.

PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit

A high-linearity and high-efficiency MMIC power amplifier is proposed that adopts a new on-chip adaptive bias control circuit, which simultaneously improves efficiency at the low output power level and linearity at the high output power level. The adaptive bias control circuit detects the input power level and supplies a low quiescent current of 16 mA at the low output power level and an increased current up to 90 mA according to the increased power level adaptively. The intelligent W-CDMA power amplifier using the adaptive bias circuit exhibits an improvement of average power usage efficiency of more than 1.93 times, and an adjacent channel leakage ratio by 4 dB at the output power of 28.3 dBm.

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An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications

A power amplifier for use in a mobile handset includes an amplifying transistor for generating an output of the mobile handset, a bias circuit having a bias transistor and providing a bias current to bias the amplifying transistor, and a bias current control circuit, responsive to a control signal, for adjusting the bias current to control an operation current of the amplifying transistor. The control signal is generated by the mobile handset, and the control signal is determined by a power level of the output of the mobile handset.

Power amplifier having a bias current control circuit

A bias control circuit for a power amplifier including an RF amplifier having a transistor for power amplification, comprises two components. A first component is a bias circuit having an active bias transistor operating in an active mode and connected to a predetermined Vref pin to provide the transistor for power amplification with a base current and a second component is a bias current control circuit having another active bias transistor connected to a predetermined Vcon pin and turned on or off depending on a high or a low mode of the Vcon pin to thereby control a base current and a quiescent current of the transistor for power amplification.

Bias control circuit for power amplifier

We report a 5 GHz linear InGaP/GaAs HBT monolithic microwave integrated circuit (MMIC) power amplifier for wireless LAN applications. The three-stage power amplifier operates with 103 mA - low quiescent current of Class AB mode using active bias circuit under a single supply of +3.3V A total current of 196(194) mA is consumed with an output power of 18 dBm and PAE (power-added efficiency) of 9.7% at 5.25(5.15) GHz. The power amplifier exhibits a power gain of 19.6 (17.8/18.5) dB, 1-dB compression point (P/sub 1/dB) of 26(25/25) dBm, and PAE of 27.8(25.4/20) % at 5.25(5.15/5.85) GHz. Measured third-order IMD(intermodulation distortion) is less than -25 dBc at 3 dB back-off and less than -30 dBc at 5 dB back-off from P/sub 1/dB for the frequency range between 5.15 and 5.85 GHz.

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Papers

PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit

An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications

Power amplifier having a bias current control circuit

Bias control circuit for power amplifier

A low quiescent current 3.3V operation linear MMIC power amplifier for 5 GHz WLAN applications