Plasma immersion ion implantation (PIII) is a cluster compatible doping and processing tool offering many inherent advantages over conventional beamline ion implantation. When first introduced in the late 1980s, the technique was primarily used to enhance the surface mechanical properties of metals. Recently, a substantial amount of research activities have focused on microelectronics and have led to a number of very interesting applications, such as the formation of shallow junction, synthesis of silicon-on-insulator, large area implantation, trench doping, conformal deposition, and so on. In this paper, we will review the principles of PIII, the dynamic sheath model for various kinds of plasma, reactor designs, recent applications in the area of microelectronics, as well as the future of PIII pertaining to semiconductor materials and processing.

Plasma immersion ion implantation—a fledgling technique for semiconductor processing

The combination of a cryogenic radiometer and synchrotron radiation enables detector scale realization in spectral regions that are otherwise difficult to access. Cryogenic radiometry is the most accurate primary detector-based standard available to date, and synchrotron radiation gives a unique broadband and continuous spectrum that extends from x ray to far IR. We describe a new cryogenic radiometer-based UV radiometry facility at the Synchrotron Ultraviolet Radiation Facility II at the National Institute of Standards and Technology. The facility is designed to perform a variety of detector and optical materials characterizations. The facility combines a high-throughput, normal incidence monochromator with an absolute cryogenic radiometer optimized for UV measurements to provide absolute radiometric measurements in the spectral range from 125 nm to approximately 320 nm. We discuss results on photodetector characterizations, including absolute spectroradiometric calibration, spatial responsivity mapping, spectroreflectance, and internal quantum efficiency. In addition, such characterizations are used to study UV radiation damage in photodetectors that can shed light on the mechanism of the damage process. Examples are also given for UV optical materials characterization.

Ultraviolet Radiometry With Synchrotron Radiation and Cryogenic Radiometer

In this paper we present a complete and analytical drain current model for surrounding gate MOSFETs. The model was developed using a quasi-two-dimensional cylindrical form of the Poisson equation and based on the drift-diffusion equation. The model applicable for digital/analog circuit simulation contains the following advanced features: precise description of the subthreshold, near threshold and above-threshold regions of operation by one single expression; single-piece drain current equation smoothly continuous from the linear region to the saturation region; considering the source/drain resistance; inclusion of important short channel effects such as velocity saturation, drain-induced barrier lowering and channel length modulation.

An analytical surrounding gate MOSFET model

https://physics.nist.gov/MajResFac/SURF/SURF/recent/surf9901.pdf

Ultraviolet radiometry with synchrotron radiation and cryogenic radiometry

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries.

An analytical fully-depleted SOI MOSFET model considering the effects of self-heating and source/drain resistance

This paper presents a new degraded drain current model for n MOSFETs with hot-carrier-induced interface states. The model was developed by starting from a two-dimensional Poisson's equation and including the effects of series resistances, carrier velocity saturation, and hot-carrier-induced interface states. The nonuniform spatial distribution of interface states is also accounted for in the model. The fitting results show good agreement between the model and the experimental data. The model provides a physics-based approach for modeling forward and reverse MOSFET characteristics with hot-carrier-induced damage and can be easily applied to simulation of device behavior after hot-carrier stress for assessment and improvement of long-term device or circuit reliability.

Modeling of hot-carrier-stressed characteristics of nMOSFETs

In a p MOSFET, trapped electrons in the gate oxide due to hot-carrier stress reduce the effective channel length by inverting the surface from an n -type surface to a p -type surface and extend the p drain region. To describe the channel shortening, this paper presents a new analytical, physics-based I - V model for hot-electron damaged submicrometer p -type MOSFETs. The model was developed based on a pseudo-two-dimensional approach, it incorporates the effect of the spatial distribution of trapped electrons and can be used to calculate the degraded channel electric field and potential distribution. The model can also describe the time-dependence of degraded drain current with stress time.

Modeling of hot-carrier stressed characteristics of submicrometer pMOSFETs

The reliability of bipolar junction transistors (BJTs) at high current densities is an important issue and requires detailed study. In the past, there have been studies on the effect of d.c. high current stress on the BJT current-voltage characteristics, but there is no report on the effect of dynamic high current stress on the BJT I-V characteristics. In this paper, we study experimentally the degradation of metal-emitter Si n-p-n and p-n-p bipolar junction transistors under dynamic high current stress and biased in open collector condition. Reduction and increase of base current at low bias voltage with increasing stress time have been found. Decrease of base and collector currents at high bias in n-p-n BJTs was found only after a large stress time has elapsed.

Degradation of bipolar junction transistors under dynamic high current stress and biased in open-collector condition

In this paper we study the effect of light illumination on the output characteristics of lightly doped drain-source (LDD) MOSFETs with channel length of 0.9 μm. In the study, the bulk terminal of the substrate is either shorted to the source or left floating. In the open (floating) case, we found the photovoltaic effect plays a dominant role, the output drain current increases with increasing light intensity. In the shorted case, the optical effect occurs when the device is biased at the subthreshold gate voltage, it is mainly due to the photo-induced conductivity modulation.

Young-Shying Chen

Papers

Modeling of hot-carrier-stressed characteristics of nMOSFETs

Modeling of hot-carrier stressed characteristics of submicrometer pMOSFETs

Degradation of bipolar junction transistors under dynamic high current stress and biased in open-collector condition

Optical effects on the current-voltage characteristics of lightly doped drain silicon MOSFETs