A correct and improved analytical subthreshold surface potential model for pocket n-MOSFETs is proposed. The model is based on solutions of the quasi-two-dimensional (quasi-2-D) Poisson's equation, which satisfy rigorously the boundary conditions of continuity of potential and electric field in the lateral direction along the surface of pocket devices. The closed-form model equations without any fitting empirical formulas efficiently and correctly generate surface potential profiles between the source and drain of deep-submicrometer as well as long-channel pocket n-MOSFETs. Drain-induced barrier lowering (DIBL) effect of deep-submicrometer pocket n-MOSFETs is also predicted by the potential model. The subthreshold surface potential model is applied to off-state current and threshold voltage of deep-submicrometer or sub-100-nm pocket n-MOSFETs.

Analytical subthreshold surface potential model for pocket n-MOSFETs

A one-region compact I/sub ds/ model from subthreshold to saturation, which resembles the same form as the well-known long-channel model but includes all major short-channel effects (SCEs) in deep-submicron (DSM) MOSFETs, has been formulated through physics-based effective transformation. The model has 23 process-dependent fitting parameters, which requires an 11-step, one-iteration extraction procedure. The new approach to modeling channel-length modulation (CLM), subthreshold diffusion current, and edge-leakage current, all in a compact form, has been verified with the 0.25-/spl mu/m experimental data. The model covers the full range of gate length (without "binning") and bias conditions, and can be correlated to true process variables for aiding technology development.

Unified MOSFET compact I-V model formulation through physics-based effective transformation

At high frequency, the MOSFET drain current noise and induced gate noise are generally accepted as dominated by the thermal noise as the MOSFET is operating in strong inversion region. However, controversy exists about the high-frequency noise in subthreshold region. This paper proposes unified high-frequency drain current noise and induced gate noise models valid in strong-, moderate- and weak-inversion regions. These models are necessary for the completeness of device noise model and helpful for low-noise high-frequency amplifier design with deep submicrometer technologies with MOSFETs operating in moderate inversion region.

A unified model for high-frequency current noise of MOSFETs

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries.

An analytical fully-depleted SOI MOSFET model considering the effects of self-heating and source/drain resistance

The importance of long term reliability in MOS VLSI circuits is becoming an important subject because of the increasing densities of VLSI chips. Hot carrier effects cause noncatastrophic failures which develop gradually over time and change the circuit performance. The Weibull distribution is often used to describe the life times of parts and widely applied to characterize the breakdown statistics of solid dielectric samples. In this study the degradation in the threshold voltage is observed experimentally by operating the MOSFET under different voltage stress conditions. Using Weibull distribution, a new approach is proposed to represent the hot carrier degradation in threshold voltage of MOS transistors. The linear regression method is used to estimate the Weibull parameters and the correlation coefficient is used to confirm the results. The observed and the estimated values of the degradation are compared and found to be in good agreement with each other. The results obtained can be easily applied to SPICE NMOS and PMOS device models, therefore the method proposed will be helpful to estimate the influence of hot carrier degradation to the performance of any analog circuit topology.

A Weibull distribution-based new approach to represent hot carrier degradation in threshold voltage of MOS transistors

In a p MOSFET, trapped electrons in the gate oxide due to hot-carrier stress reduce the effective channel length by inverting the surface from an n -type surface to a p -type surface and extend the p drain region. To describe the channel shortening, this paper presents a new analytical, physics-based I - V model for hot-electron damaged submicrometer p -type MOSFETs. The model was developed based on a pseudo-two-dimensional approach, it incorporates the effect of the spatial distribution of trapped electrons and can be used to calculate the degraded channel electric field and potential distribution. The model can also describe the time-dependence of degraded drain current with stress time.

Modeling of hot-carrier stressed characteristics of submicrometer pMOSFETs

Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi two-dimensional (2-D) Poisson equation. The important short-channel device features: drain-induced-barrier-lowering (DIBL), channel-length modulation (CLM), velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data.

A compact LDD MOSFET I-V model based on nonpinned surface potential

In this paper, we present a non-local gate current model for sub-micron lightly doped drain (LDD) and single-drain (SD) MOSFETs. Using this model and a trapping charge mechanism, we can calculate the spatial oxide trapping charge due to the electron transport in the oxide. This model is developed by using a modified lucky electron concept to include the quantum-mechanical tunneling effect. The channel electric field is first calculated by using an analytical pseudo-2-D MOSFET model, the spatial distribution of electron temperature is generated, and the electron temperature is then derived by using a simplified energy balance equation. From the electron temperature, we calculate the spatial gate current density, and using a first-order charge trapping mechanism, we finally calculate the distribution of non-local oxide trapping charge. This model is a time-saving CAD model and is physics transparent.

A non-local gate current and oxide trapping charge generation model for lightly doped drain and single-drain nMOSFETs

In this paper, we present a complete and physics-based drain current model for hot-carrier damaged fully depleted silicon-on-insulator (SOI) p-type metal-oxide-semiconductor-field-effect-transistors (pMOSFETs). Experimentally, it was found that the post-stress drain current of SOI pMOSFETs increases, this is caused by hot-carrier-induced electron trapping in the oxide. We present an electron gate current model and use an oxide trapping mechanism for calculating the spatial distribution of oxide-trapping-charges, which are substituted into the damaged SOI MOSFET drain current model, then we can model the hot-carrier damaged drain current. To calculate the electron gate current in pMOSFETs at low gate bias, a complete electron gate current considering the subthreshold operation is developed.

Modeling of electron gate current and post-stress drain current of p-type silicon-on-insulator MOSFETs

In this paper, we report a model for calculating the gate current as a function of gate and drain biases by considering the quantum-mechanical effect Using a WKB approximation for the transmission probability, direct and Fowler–Nordheim tunneling currents across thin gate oxides of MOSFETs have been modeled for carriers from the inversion layers in Si substrate The modeled direct tunneling currents have been compared to experimental data obtained from MOSFETs with oxide thickness of 2 nm The gate current model is developed by using a pseudo-2D and analytical drain current model as a basis to generate channel electric field and electron temperature, which is derived using a simplified energy balance equation From the electron temperature, we can calculate the non-local gate current This model is a time-saving CAD model

Chorng-Jye Sheu

Papers

Modeling of hot-carrier stressed characteristics of submicrometer pMOSFETs

A compact LDD MOSFET I-V model based on nonpinned surface potential

A non-local gate current and oxide trapping charge generation model for lightly doped drain and single-drain nMOSFETs

Modeling of electron gate current and post-stress drain current of p-type silicon-on-insulator MOSFETs

A MOSFET gate current model with the direct tunneling mechanism