Communication at millimeter wave (mmWave) frequencies is defining a new era of wireless communication. The mmWave band offers higher bandwidth communication channels versus those presently used in commercial wireless systems. The applications of mmWave are immense: wireless local and personal area networks in the unlicensed band, 5G cellular systems, not to mention vehicular area networks, ad hoc networks, and wearables. Signal processing is critical for enabling the next generation of mmWave communication. Due to the use of large antenna arrays at the transmitter and receiver, combined with radio frequency and mixed signal power constraints, new multiple-input multiple-output (MIMO) communication signal processing techniques are needed. Because of the wide bandwidths, low complexity transceiver algorithms become important. There are opportunities to exploit techniques like compressed sensing for channel estimation and beamforming. This article provides an overview of signal processing challenges in mmWave wireless systems, with an emphasis on those faced by using MIMO communication at higher carrier frequencies.

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

Hybrid analog/digital MIMO architectures were recently proposed as an alternative for fully-digitalprecoding in millimeter wave (mmWave) wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open loop compressive channel estimation technique which is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimated, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the trade-offs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?

At the turn of this century, there was widespread concern that the performance of analog-to-digital converters (ADCs) might have reached a saturation point and would, in fact, deteriorate as we began to scale into deep submicron CMOS technology. The past 15 years of innovation have clearly refuted such fears. Driven by a combination of application pull, architectural modifications, and relentless optimization, we have seen steady improvements in several key performance metrics.

The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories

Today's applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates and high resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, this structure suffers from mismatches between the sub-converters, which cause errors on the output signal, and more significantly, decrease the SFDR. These mismatches can be a severe limitation in applications such as satellite reception, where both narrowband and wideband signals are used. This paper introduces digital derivative-based estimation of timing mismatches. Gain, offset and skew mismatch calibrations are performed entirely in the digital domain through equalization.

/pdf/22-5-a-1-62gs-s-time-interleaved-sar-adc-with-digital-56x65b2jk1.pdf

22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS

A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-leakage digital process. A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this work to attain high conversion throughput and power savings at the same time using a simple, low-gain ( $\sim$ 30 dB) residue amplifier. The overall architecture and the digital calibration also enable the downsizing of the first SAR stage to that of the kT/C limit, yielding a wideband input network delivering an over 80 dB spurious-free dynamic range (SFDR) while digitizing a 300 MHz input at 160 MS/s. The core ADC consumes 4.96 mW and occupies an area of 0.042 mm $^{2}$ ; the calibration circuits dissipate 0.1 mW (estimated). An 86.9 dB SFDR and a 66.7 dB signal-to-noise plus distortion ratio (SNDR) were measured with a 2 V $_{\rm pp}$ , 5 MHz sine-wave input at full speed. The ADC achieves a Walden figure-of-merit (FoM) of 20.7 fJ/conversion-step with a Nyquist input.

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector

Over the last years several low-power time-interleaved (TI) ADC designs in the 2.5-to-3.0GS/s range have been published [1-3], intended for integration in applications like radar, software-defined radio, full-spectrum cable modems, and multi-channel satellite reception. It is to be expected that future generations of these applications will require a higher ADC sampling rate, while maintaining good high-frequency linearity. Furthermore, a high spectral purity is desired, as spurs can cause an SNR degradation of several dB for weak narrowband signals. For interleaved converters, this mandates an output with limited interleaving artifacts. For the reception of broadband and multi-carrier signals, the gain mismatch and time-skew tones do not typically limit performance, since the spurs are evenly spread over frequency due to the broadband nature of the input signal. The offset mismatches, however, generate spurs at fixed frequencies, thereby representing the main performance limitation. This paper presents a prototype 3.6GS/s 11b TI SAR ADC with a THD that is better than -55dB at 2.5GHz and that has gain and offset spurs below -80dBFS, consuming 795mW in 65nm CMOS.

An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS

This paper presents a dynamic latched comparator suitable for applications with very low supply voltage. It adopts a circuit topology with a separated input stage and two cross-coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This circuit topology enables fast operation over a wide input common-mode voltage and supply voltage range. This comparator is designed in 65-nm CMOS technology with standard threshold transistors (V T ≈0.4V). Simulation shows that it achieves 5mV sensitivity for a sampling rate of 5GS/s with 1.2V supply voltage, 10mV for 250MS/s with 0.5V supply voltage and 100MS/s with 0.45V supply voltage. The simulated delay time of the proposed comparator is about 30% shorter than the dual-tail dynamic comparator with 0.5V supply voltage and only one third compared to that of the conventional one with 0.6V supply voltage when they are designed to have a similar input referred offset voltage in 65nm CMOS technology.

A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS

This paper presents a parallel sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals efficiently by exploiting the statistical properties of these signals. With this technique, the input signal power of an ADC can be boosted without getting excessive clipping distortion and the ADC can have a higher resolution over the critical small amplitude region. Hence the overall signal to noise and clipping distortion ratio is improved. This technique allows reducing power dissipation and area in comparison to conventional solutions for converting multi-carrier signals. As an example, an 11b switched-capacitor pipeline ADC with the parallel sampling technique applied to its first stage is implemented in CMOS 65 nm technology. It achieves a full-scale input signal range of 2 V differentially with a 1.2 V supply voltage. Simulations show an improvement of more than 5 dB in signal-to-noise-and-clipping-distortion ratio (SNCDR) and around 8 dB in dynamic range (DR) compared to a conventional 11b ADC for converting multi-carrier signals and achieve a comparable SNCDR and noise power ratio (NPR) as a conventional 12b pipeline for converting multi-carrier signals with less than half the power and area.

An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals

This paper presents an 11b 1GS/s ADC with a parallel sampling architecture to enhance SNDR for broadband multi-carrier signals. It contains two 1GS/s 11b sub-ADCs each achieving > 54dB SNDR for input frequencies up to Nyquist frequency and state-of-the-art linearity performance. The SNDR of the ADC with the parallel sampling architecture is improved by 5dB compared to its sub-ADCs when digitizing multi-carrier signals with large crest factors. This improvement is achieved at less than half the cost in power and area compared to the conventional approach. The chip is implemented in 65nm LP CMOS and consumes in total 350mW at 1GS/s.

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals

This paper presents a dual sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals more efficiently and proposes an 11b switched-capacitor pipeline ADC based on this technique. With the dual sampling technique, the input signal power of the ADC can be boosted without getting excessive clipping noise and the ADC can have a higher resolution over the critical low amplitude region. Hence the overall signal to thermal, quantization and clipping noise ratio is improved. The 11b pipeline ADC with the proposed technique achieves a wide input signal range of 2Vppd using a single 1.2V supply. Simulations show an improvement of about 5dB in SNDR and better than 10dB in MTPR compared to a conventional 11b ADC for converting multi-carrier signals.

/pdf/an-11b-pipeline-adc-with-dual-sampling-technique-for-3hjeut88le.pdf

Yu Lin

Papers

An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS

A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS

An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals

An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals