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Yuan Xie

Researcher at University of California, Santa Barbara

Publications -  794
Citations -  32484

Yuan Xie is an academic researcher from University of California, Santa Barbara. The author has contributed to research in topics: Computer science & Cache. The author has an hindex of 76, co-authored 739 publications receiving 24155 citations. Previous affiliations of Yuan Xie include Pennsylvania State University & Foundation University, Islamabad.

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Proceedings Article

Weakly Supervised Salient Object Detection Using Image Labels.

TL;DR: Zhang et al. as discussed by the authors proposed to use the combination of a coarse salient object activation map from the classification network and saliency maps generated from unsupervised methods as pixel-level annotation, and developed a simple yet very effective algorithm to train fully convolutional networks for salient object detection supervised by these noisy annotations.
Proceedings ArticleDOI

Unifying visual saliency with HOG feature learning for traffic sign detection

TL;DR: Experimental results show that, the proposed approach can achieve robustness to illumination, scale, pose, viewpoint change and even partial occlusion and achieve computational parsimony using improved Model of Saliency-Based Visual Attention.
Proceedings ArticleDOI

Allocation and scheduling of conditional task graph in hardware/software co-synthesis

TL;DR: An allocation and scheduling algorithm that efficiently handles conditional execution in multi-rate embedded system and a mutual exclusion detection algorithm that helps the scheduling algorithm to exploit the resource sharing is introduced.
Journal ArticleDOI

Design Space Exploration for 3-D Cache

TL;DR: This paper presents a delay and energy model 3D cache delay-energy estimation tool (3D-Cacti), which allows partitioning of a cache across different device layers at various levels of granularity, and explores the architectural design of cache memories using 3D circuits.
Proceedings ArticleDOI

Design trade-offs for high density cross-point resistive memory

TL;DR: A comprehensive analysis of issues related to reliability, energy consumption, area overhead, and performance of the cross-point arrays of Resistive RAM, and discusses different programming schemes specifically suited for cross- point arrays.