A high-throughput programmable fast Fourier transform (FFT) processor is designed supporting 16- to 4096-point FFTs and 12- to 2400-point discrete Fourier transforms (DFTs) for 4G, wireless local area network, and future 5G. A 16-path data parallel memory-based architecture is selected as a tradeoff between throughput and cost. To implement a hardware-efficient high-speed processor, several improvements are provided. To maximally reuse the hardware resource, a reconfigurable butterfly unit is proposed to support computing including eight radix-2 in parallel, four radix-3/4 in parallel, two radix-5/8 in parallel, and a radix-16 in one clock cycle. Twiddle factor multipliers using different schemes are optimized and compared, wherein modified coordinate rotation digital computer scheme is finally implemented to minimize the hardware cost while supporting both FFTs and DFTs. An optimized conflict-free data access scheme is also proposed to support multiple butterflies at any radices. The processor is designed as a general IP and can be implemented using a processor synthesizer (application-specific instruction-set processor designer). The electronic design automation synthesis result based on a 65-nm technology shows that the processor area is 1.46 mm2. The processor supports 972 MS/s 4096-point FFT at 250 MHz with a power consumption of 68.64 mW and a signal-to-quantization-noise ratio of 66.1 dB. The proposed processor has better-normalized throughput per area unit than the state-of-the-art available designs.

A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G

The fast Fourier transform (FFT) is a widely used algorithm in signal processing applications. FFT hardware architectures are designed to meet the requirements of the most demanding applications in terms of performance, circuit area, and/or power consumption. This chapter summarizes the research on FFT hardware architectures by presenting the FFT algorithms, the building blocks in FFT hardware architectures, the architectures themselves, and the bit reversal algorithm.

Hardware architectures for the fast Fourier transform

A considerable part of latency in the baseband of massive multiple-input multiple-output (MIMO) systems is introduced by orthogonal frequency division multiplexing (OFDM) (de)modulation. To address the low-latency demand of massive MIMO systems, a fast Fourier transform (FFT) processor and corresponding reordering scheme are proposed, which reduce the processing latency and reordering latency of OFDM-based systems, respectively. The main idea is to utilize the OFDM guard bands to decrease the number of required computations and thus the processing time. In case of a 2048-point IFFT, the proposed scheme leads to 42% reduction in latency compared to the reported pipelined schemes at the cost of 4% additional memory, which is around 2.4% of the total chip area. To realize this idea, a modified pipelined architecture with a reorganized memory structure and also an efficient data scheduling mechanism for memories and butterflies are developed. Using the proposed scheme, a 2048-point FFT/IFFT processor has been implemented in a 28-nm complementary metal-oxide-semiconductor technology. The post-layout simulations show that our design achieves a throughput of 0.6 GS/s and 1200 clock cycles latency, the lowest latency reported to-date for single-input pipelined FFT/IFFT architectures.

A Low Latency FFT/IFFT Architecture for Massive MIMO Systems Utilizing OFDM Guard Bands

Time-interleaving (TI) is a major trend for high-speed ADC designs. The major limitation of TI-ADC is the mismatches among ADC channels. Calibration techniques have been actively pursued to compensate the mismatches. In this paper, we present a new spectral calibration technique for TI-ADC. Although the technique does not run in the background, it does not need external calibration signals and has no constraint on the input signal, which is similar to blind estimation. Compared to benchmark designs, the new technique involves much less calibration hardware overhead, and calibrates all mismatches with much less time. In practice, this efficient technique can run repetitively to track the environment changes. It addresses the needs from practical TI-ADCs well. The technique is verified with extensive simulations on a 2GS/s 12-bit 16-channel ADC. With mismatch spurs over −40dBc, the technique can reliably suppress the spurs to be lower than −80dBc within about 4000 samples without the need of iteration.

An Efficient Spur-Aliasing-Free Spectral Calibration Technique in Time-Interleaved ADCs

In this paper, we propose a flexible and reconfigurable changeable-radix fast Fourier transform (FFT) hardware architecture. It aims to support 48 different FFT sizes and up to 4096 FFT points, which are defined in current 3GPP-LTE communication system. The built-up design structure is primarily constructed on a radix-52 basis of single-path delay feedback FFT and up to 18 various changeable radixes of FFT processing. A design technique of switchable FIFO usage approach is developed to efficiently manage FIFO arrangement for 48 FFT modes. In addition, a design technique of coarse and fine rotating is designed to effectively reduce twiddle-factor circuit area. By using TSMC 40-nm CMOS technology, an FFT ASIC implementation only has a core area occupation of 0.414 mm2 and consumes 49.8 mW in average at maximal working frequency of 526.32 MHz. This innovative design work is competitive as compared to current state-of-the-art works, especially in terms of circuit area cost and power/energy performance evaluation.

Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements

This paper presents a reconfigurable fast Fourier transform (FFT) hardware architecture, supporting 46 different FFT sizes defined in 3GPP-LTE applications. Our proposed design concept is mainly based on combined radix-5, radix-32, and radix24 single-path delay feedback FFT design approaches. In addition, in order to elaborate our hardware design, we also develop three design techniques, such as reconfigurable processing kernel with seven types (RPK-ST), efficient FIFO management scheme, and single-table approximation method. In an ASIC implementation with TSMC 40-nm CMOS technology, our 46-mode reconfigurable FFT chip only occupies a core area of 0.36 mm2, dissipates 48.46 mW, and operates up to clock frequency of 500 MHz. As compared with the other state-of-the-art works, our work delivers high-quality design results in the aspects of area- and energy-related performance indexes, providing a constructive FFT design prototyping for 3GPP-LTE systems.

VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications

In this paper, we propose a reconfigurable (RC) fast Fourier transform (FFT) design in a systematic design scheme. The RC design bricks are mainly proposed to arbitrarily concatenate to support FFT-point required. Meanwhile, we show three developed design techniques, including six-type RC processing element, systematic first-in first-out reuse arrangement, and section-based twiddle factor generator to elaborate our FFT design. In a design/implementation example, it can support up to 2187 FFT-point manipulation and 48 RC modes. It also supports 32 operating modes defined in 3GPP-LTE standard. In application-specified integrated circuit implementation with TSMC 90-nm CMOS technology, our design work occupies a core area of 1.664 mm2 and consumes 35.2 mW under maximal clock frequency of 188.67 MHz. This paper also has outstanding design performance in terms of speed-area ratio and power-frequency ratio for comparison reference.

48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches

In this paper, we propose a cost-efficient hardware design, coarse and fine rotation (CFR) based FFT twiddle factor generator. It aims to extremely reduce the hardware area, especially for the larger length of FFT-points. Also, our proposed approach is generalized for arbitrary FFT sizes, not limited to the power of 2. In hardware implementation by using TSMC 90-nm CMOS technology, the circuit area saving ratio is up to 93.7% for the 16384-point FFT design example.

Cost-efficient hardware design of coarse and fine rotation based FFT twiddle factor generator for 3GPP LTE applications

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm2 and dissipates 233.5 mW at maximal operating frequency of 250 MHz. Keywords—Reconfigurable, fast Fourier transform, single-path delay feedback, 3GPP-LTE.

Yue-Qu Liu

Papers

VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications

48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches

Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements

Cost-efficient hardware design of coarse and fine rotation based FFT twiddle factor generator for 3GPP LTE applications

A Low-Area Fully-Reconfigurable Hardware Design of Fast Fourier Transform System for 3GPP-LTE Standard