High-performance graphene transistors for radio frequency applications have received much attention and significant progress has been achieved. However, devices based on large-area synthetic graphene, which have direct technological relevance, are still typically outperformed by those based on mechanically exfoliated graphene. Here, we report devices with intrinsic cutoff frequency above 300 GHz, based on both wafer-scale CVD grown graphene and epitaxial graphene on SiC, thus surpassing previous records on any graphene material. We also demonstrate devices with optimized architecture exhibiting voltage and power gains reaching 20 dB and a wafer-scale integrated graphene amplifier circuit with voltage amplification.

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State-of-the-art graphene high-frequency electronics.

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

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Noise modeling for RF CMOS circuit simulation

The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET f/sub T/, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated common-source LNA (CSLNA). A capacitor cross-coupled g/sub m/-boosting scheme is described that improves the NF and retains the advantages of the CGLNA topology. The technique also enables a significant reduction in current consumption. A fully integrated capacitor cross-coupled CGLNA implemented in 180-nm CMOS validates the g/sub m/-boosting technique. It achieves a measured NF of 3.0 dB at 6.0 GHz and consumes only 3.6 mA from 1.8 V; the measured input-referred third-order intercept ( IIP3) value is 11.4 dBm. The capacitor cross-coupled g/sub m/-boosted CGLNA is attractive for low-power fully integrated applications in fine-line CMOS technologies.

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A capacitor cross-coupled common-gate low-noise amplifier

This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization issues for emerging reconfigurable multiband/multistandard and wideband transceivers. Furthermore, we highlight the impact of CMOS technology scaling on linearity and outline how to design a linear LNA in a deep submicrometer process. Finally, general design guidelines for high-linearity LNAs are provided.

Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Foreword. Preface. List of Symbols. 1. Introduction. 1.1 The Importance of Device Modeling for IC Design. 1.2 A Short History of the EKV MOST Model. 1.3 The Book Structure. PART I: THE BASIC LONG-CHANNELINTRINSIC CHARGE-BASED MODEL. 2. Introduction. 2.1 The N-channel Transistor Structure. 2.2 Definition of charges, current, potential and electric fields. 2.3 Transistor symbol and P-channel transistor. 3. The Basic Charge Model. 3.1 Poisson's Equation and Gradual Channel Approximation. 3.2 Surface potential as a Function of Gate Voltage. 3.3 Gate Capacitance. 3.4 Charge Sheet Approximation. 3.5 Density of Mobile Inverted Charge. 3.6 Charge-Potential Linearization. 4. Static Drain Current. 4.1 Drain Current Expression. 4.2 Forward and Reverse Current Components. 4.3 Modes of Operation. 4.4 Model of Drain Current Based on Charge Linearization. 4.5 Fundamental Property: Validity and Application. 4.6 Channel Length Modulation. 5. The Small-Signal Model. 5.1 The Static Small-Signal Model. 5.2 A General Non-Quasi-Static Small-Signal Model. 5.3 The Quasi-Static Dynamic Small-Signal Model. 6. The Noise Model. 6.1 Noise Calculation Methods. 6.2 Low-Frequency Channel Thermal Noise. 6.3 Flicker Noise. 6.4 Appendices. Appendix : The Nyquist and Bode Theorems. Appendix : General Noise Expression. 7. Temperature Effects and Matching. 7.1 Introduction. 7.2 Temperature Effects. PART II: THE EXTENDED CHARGE-BASED MODEL. 8. Non-Ideal Effects Related to the Vertical Dimension. 8.1 Introduction. 8.2 Mobility Reduction Due to the Vertical Field. 8.3 Non-Uniform Vertical Doping. 8.4 Polysilicon Depletion. 8.4.1 Definition of the Effect. 8.5 Band Gap Widening. 8.6 Gate Leakage Current. 9. Short-Channel Effects. 9.1 Velocity Saturation. 9.2 Channel Length Modulation. 9.3 Drain Induced Barrier Lowering. 9.4 Short-Channel Thermal Noise Model. 10. The Extrinsic Model. 10.1 Extrinsic Part of the Device. 10.2 Access Resistances. 10.3 Overlap Regions. 10.4 Source and Drain Junctions. 10.5 Extrinsic Noise Sources. PART III: THE HIGH-FREQUENCY MODEL. 11. Equivalent Circuit at RF. 11.1 RF MOS Transistor Structure and Layout. 11.2 What Changes at RF?. 11.3 Transistor Figures of Merit. 11.4 Equivalent Circuit at RF. 12. The Small-Signal Model at RF. 12.1 The Equivalent Small-Signal Circuit at RF. 12.2 Y-Parameters Analysis. 12.3 The Large-Signal Model at RF. 13. The Noise Model at RF. 13.1 The HF Noise Parameters. 13.2 The High-Frequency Thermal Noise Model. 13.3 HF Noise Parameters of a Common-Source Amplifier. References. Index.

Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design

This paper presents the basis of the modeling of the MOS transistor for circuit simulation at radio-frequency (RF). A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. In addition to the intrinsic device and the source and drain series resistance, the model also has a gate resistance, that is fundamental to correctly model the frequency and noise behavior. The subcircuit also includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance y 22. The bias and geometry dependence of all the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y-parameters, the transit frequency and the maximum oscillation frequency are established and compared to measurements made on a 0.25 p m CMOS process. The Y-parameters and transit frequency simulated with this scalable model versus frequency, geometry and bias are in good agreement with measured data The non-quasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced and compared to noise models available in BSIM3v3. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices.

MOS Transistor Modeling Issues for RF Circuit Design

Analytical models for the induced gate noise and its correlation with the channel noise of MOSFETs including the channel-length modulation effect for radio-frequency integrated circuits are presented and verified with experiments. In addition, the implementation of the enhanced channel noise and the induced gate noise based on any compact MOSFET model using sub-circuit technique is described.

MOSFET drain and induced-gate noise modeling and experimental verification for RF IC design

In this paper, we discuss some important issues in MOSFET modeling for radio-frequency (RF) integrated-circuit (IC) design. We start with the introduction of the basics of RF modeling. A simple sub-circuit model is presented with comparisons of the data for both y parameter and f/sub T/ characteristics. Good model accuracy is achieved against the measurements for a 0.25 /spl mu/m RF CMOS technology. The high frequency (HF) noise modeling issues are also discussed. A methodology to extract the channel thermal noise of MOSFETs from the HF noise measurements is presented and the concept of induced-gate noise is discussed briefly. The results of different noise modeling approaches are also given with the comparison of the measured data, with which the prediction capability of the HF noise behavior of any modeling approach can be examined.

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MOSFET modeling for RF circuit design

High frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit (IC) design is discussed. Equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. Modeling of the intrinsic device and the extrinsic components is disussed by accounting for the important physical effects at both DC and HF. Based on the Y-parameter analysis of the equivalent circuit model, procedures of the HF model parameter extraction are also developed. With the discussed approaches, a sub-circuit RF model incorporating the modeling of parasitics is presented. This model is compared with the measured data for both y parameter and fr characteristics. Good model accuracy is achieved against the measurements for a 0.25μm RF CMOS technology. The non-quasi-static (NQS) modeling issue has also been discussed by using the BSIM3v3 based RF model to predict the HF characteristics of devices with serious NQS effects. Further, noise modeling issues are discussed by analyzing the theoretical and experimental results in both the flicker noise and thermal noise modeling. Modeling efforts to in corporate new physical effects are needed to predict better the flicker noise characteristics in today's MOSFETs. A detailed analysis of the HF noise parameters has been conducted to establish the relationship between the noise parameters preferred by circuit designers and obtained by HF noise measurement. Analytical calcultion of the noise parameters has also been discussed to understand the noise characteristics with/without some parasitic components such as gate and substrate resistances as well as the influence of the induced gate noise. The HF noise predictivities of several HF noise models are also examined with the measured data. The results show that the BSIM3v3 based RF model can predict the channel thermal noise better than the other models.

MOSFET modeling for RF IC design

An extraction method to obtain the channel thermal noise in MOSFETs directly from DC, scattering parameter and RF noise measurements is presented. In this extraction method, the transconductance (g/sub m/), output resistance (R/sub DS/), and source and drain resistances (R/sub S/ and R/sub D/) are obtained from DC measurements. The gate resistance (R/sub G/) is extracted from scattering-parameter measurements, and the equivalent noise resistance (R/sub n/) is obtained from RF noise measurements. This method has been verified by using the measured data of a 0.36 /spl mu/m n-type MOSFET up to 18 GHz.

Yuhua Cheng

Papers

MOS Transistor Modeling Issues for RF Circuit Design

MOSFET drain and induced-gate noise modeling and experimental verification for RF IC design

MOSFET modeling for RF circuit design

MOSFET modeling for RF IC design

Extraction of the channel thermal noise in MOSFETs