The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET f/sub T/, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated common-source LNA (CSLNA). A capacitor cross-coupled g/sub m/-boosting scheme is described that improves the NF and retains the advantages of the CGLNA topology. The technique also enables a significant reduction in current consumption. A fully integrated capacitor cross-coupled CGLNA implemented in 180-nm CMOS validates the g/sub m/-boosting technique. It achieves a measured NF of 3.0 dB at 6.0 GHz and consumes only 3.6 mA from 1.8 V; the measured input-referred third-order intercept ( IIP3) value is 11.4 dBm. The capacitor cross-coupled g/sub m/-boosted CGLNA is attractive for low-power fully integrated applications in fine-line CMOS technologies.

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A capacitor cross-coupled common-gate low-noise amplifier

This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-/spl mu/m CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement.

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MOS transistor modeling for RF IC design

A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-/spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications.

A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-mum 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7plusmn0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets

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A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

This brief presents a new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs. Based on the new channel noise model, the simulated noise spectral densities of the devices fabricated in a 0.18 /spl mu/m CMOS process as a function of channel length and bias condition are compared to the channel noise directly extracted from RF noise measurements. In addition, the hot electron effect and the noise contributed from the velocity saturation region are discussed.

Channel noise modeling of deep submicron MOSFETs

An extraction method to obtain the induced gate noise (i~/sub g/~/sup 2/~) channel noise (i~/sub d/~/sup 2/~), and their cross correlation (i~/sub g/~i~/sub d/~*~) in submicron MOSFETs directly from scattering and RF noise measurements has been presented and verified by measurements. In addition, the extracted induced gate noise, channel noise, and their correlation in MOSFETs fabricated in 0.18-/spl mu/m CMOS process versus frequencies, bias conditions, and channel lengths are presented and discussed.

Extraction of the induced gate noise, channel noise, and their correlation in submicron MOSFETs from RF noise measurements

High-frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit (IC) design is discussed. A subcircuit RF model incorporating the HF effects of parasitics is presented. This model is compared with the measured data for both y parameter and f/sub T/ characteristics. Good model accuracy is achieved against measurements for a 0.25 /spl mu/m RF CMOS technology. The HF noise predictivity of the model is also examined with measured data. Furthermore, a methodology to extract the channel thermal noise of MOSFETs from HF noise measurements is presented. By using the extracted channel thermal noise, any thermal noise models can be verified directly. Several noise models including the RF model discussed in this paper have been examined, and the results show that the RF model can predict the channel thermal noise better than the other models.

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High-frequency small signal AC and noise modeling of MOSFETs for RF IC design

This paper provides an overview of important issues in CMOS MOSFET modeling for radio frequency (RF) applications. Beginning with a brief review of state-of-the-art of RF CMOS technology, we discuss modeling issues that need to be resolved to meet the requirements from circuit designers. Then, we present our current achievements and activities in compact MOSFET modeling for RF circuit design.

RF modeling issues of deep-submicron MOSFETs for circuit design

An extraction method to obtain the induced gate noise (i/sub g/i/sub g//sup */), channel thermal noise (i/sub d/i/sub d//sup */) and their cross-correlation (i/sub g/i/sub d//sup */) in submicron MOSFETs directly from scattering and RF noise parameter measurements is presented and experimentally verified. In addition, the extracted induced gate noise, channel thermal noise and their correlation versus frequency, bias condition and channel length are presented.

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Extraction of the induced gate noise, channel thermal noise and their correlation in sub-micron MOSFETs from RF noise measurements

In this paper, we discuss some important issues in MOSFET modeling for radio-frequency (RF) integrated-circuit (IC) design. We start with the introduction of the basics of RF modeling. A simple sub-circuit model is presented with comparisons of the data for both y parameter and f/sub T/ characteristics. Good model accuracy is achieved against the measurements for a 0.25 /spl mu/m RF CMOS technology. The high frequency (HF) noise modeling issues are also discussed. A methodology to extract the channel thermal noise of MOSFETs from the HF noise measurements is presented and the concept of induced-gate noise is discussed briefly. The results of different noise modeling approaches are also given with the comparison of the measured data, with which the prediction capability of the HF noise behavior of any modeling approach can be examined.

/pdf/mosfet-modeling-for-rf-circuit-design-2cit1w6agl.pdf

M. Matloubian

Papers

Extraction of the induced gate noise, channel noise, and their correlation in submicron MOSFETs from RF noise measurements

High-frequency small signal AC and noise modeling of MOSFETs for RF IC design

RF modeling issues of deep-submicron MOSFETs for circuit design

Extraction of the induced gate noise, channel thermal noise and their correlation in sub-micron MOSFETs from RF noise measurements

MOSFET modeling for RF circuit design