Yun-Fang Hou

Proceedings ArticleDOI

Sub-60mV-swing negative-capacitance FinFET without hysteresis

TL;DR: In this article, negative-Capacitance FinFETs with a floating internal gate are reported, where ALD Hf042ZrO2 ferroelectricity is added on top of the gate stack.

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Proceedings ArticleDOI

TMD FinFET with 4 nm thin body and back gate control for future low power technology

Min-Cheng Chen, +21 more

TL;DR: In this paper, a 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is proposed and demonstrated for the first time, where the TMD FinFet channel is deposited by CVD.

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Proceedings ArticleDOI

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for V th matching and CMOS-compatible 3DFETs

Min-Cheng Chen, +18 more

TL;DR: In this article, a hybrid Si/MoS 2 channels were developed using a fully CMOS-compatible process using stackable 3DFETs such as FinFETs.

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Proceedings ArticleDOI

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

Yao-Jen Lee, +27 more

TL;DR: In this article, a junctionless fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike anneeling (COLSA) is demonstrated and studied.

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Proceedings Article

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

Min-Cheng Chen, +23 more

TL;DR: For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline.

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Papers

Sub-60mV-swing negative-capacitance FinFET without hysteresis

TMD FinFET with 4 nm thin body and back gate control for future low power technology

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for V th matching and CMOS-compatible 3DFETs

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin