An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

Spin transistors are a new concept device that unites an ordinary transistor with the useful functions of a spin (magnetoresistive) device. They are expected to be a building block for novel integrated circuits employing spin degrees of freedom. The interesting features of spin transistors are nonvolatile information storage and reconfigurable output characteristics: these are very useful and suitable functionalities for various new integrated circuit architectures that are inaccessible to ordinary transistor circuits. This article reviews the current status and outlook of spin transistors from the viewpoint of integrated circuit applications. The device structure, operating principle, performance, and features of various spin transistors are discussed. The fundamental and key phenomena/technologies for spin injection, transport, and manipulation in semiconductors and the integrated circuit applications of spin transistors to nonvolatile logic and reconfigurable logic are also described.

Spin-Transistor Electronics: An Overview and Outlook

This review presents the recent progress in computational materials design, experimental realization, and control methods of spinodal nanodecomposition under three- and two-dimensional crystal-growth conditions in spintronic materials, such as magnetically doped semiconductors. The computational description of nanodecomposition, performed by combining first-principles calculations with kinetic Monte Carlo simulations, is discussed together with extensive electron microscopy, synchrotron radiation, scanning probe, and ion beam methods that have been employed to visualize binodal and spinodal nanodecomposition (chemical phase separation) as well as nanoprecipitation (crystallographic phase separation) in a range of semiconductor compounds with a concentration of transition metal (TM) impurities beyond the solubility limit. The role of growth conditions, codoping by shallow impurities, kinetic barriers, and surface reactions in controlling the aggregation of magnetic cations is highlighted. According to theoretical simulations and experimental results the TM-rich regions appear in the form of either nanodots (the dairiseki phase) or nanocolumns (the konbu phase) buried in the host semiconductor. Particular attention is paid to Mn-doped group III arsenides and antimonides, TM-doped group III nitrides, Mn- and Fe-doped Ge, and Cr-doped group II chalcogenides, in which ferromagnetic features persisting up to above room temperature correlate with the presence of nanodecomposition and account for the application-relevant magneto-optical and magnetotransport properties of these compounds. Finally, it is pointed out that spinodal nanodecomposition can be viewed as a new class of bottom-up approach to nanofabrication.

Spinodal nanodecomposition in semiconductors doped with transition metals

Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or low-voltage power-on operation with the capability of power-off nonvolatile data storage. However, the two-macro approach suffers from slow store/restore speeds due to word-by-word serial transfer of data between the volatile and nonvolatile memories. Slow store/restore speeds require long power-on/off time and leave the device vulnerable to sudden power failure . This study proposes a resistive memory (memristor) based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/restore energy consumption, and a compact cell area. This resistive nonvolatile 8T2R (Rnv8T) cell includes two fast-write memristor (RRAM) devices vertical-stacked over the 8T, and a novel 2T memristor-switch, which provides both memristor control and SRAM write-assist functions. The write assist feature enables the Rnv8T cell to use read favored transistor sizing to prevent read/write failure at lower VDDs. We also fabricated the first macro-level memristor-based (or RRAM-based) nonvolatile SRAM. This 16 Kb Rnv8T macro achieved the lowest store energy and R/W VDDmin (0.45 V) of any nonvolatile SRAM or two-macro solution.

Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications

Developing a means by which to compete with commonly used Si-based memory devices represents an important challenge for the realization of future three-dimensionally stacked crossbar-array memory devices with multifunctionality. Therefore, oxide-based resistance switching memory (ReRAM), with its associated phenomena of oxygen ion drifts under a bias, is becoming increasingly important for use in nanoscalable crossbar arrays with an ideal memory cell size due to its simple metal–insulator–metal structure and low switching current of 10–100 μA. However, in a crossbar array geometry, one single memory element defined by the cross-point of word and bit lines is highly susceptible to unintended leakage current due to parasitic paths around neighboring cells when no selective devices such as diodes or transistors are used. Therefore, the effective complementary resistive switching (CRS) features in all Ti-oxide-based triple layered homo Pt/TiOx/TiOy/TiOx/Pt and hetero Pt/TiOx/TiON/TiOx/Pt geometries as alternative resistive switching matrices are reported. The possible resistive switching nature of the novel triple matrices is also discussed together with their electrical and structural properties. The ability to eliminate both an external resistor for efficient CRS operation and a metallic Pt middle electrode for further cost-effective scalability will accelerate progress toward the realization of cross-bar ReRAM in this framework.

Oxygen Ion Drift-Induced Complementary Resistive Switching in Homo TiOx/TiOy/TiOx and Hetero TiOx/TiON/TiOx Triple Multilayer Frameworks

The power-gating (PG) ability of the authors' previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-spin-transistors with spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-spin-transistor parts of the cell. The NV-DFF is applicable to coarse- and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.

Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems

The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin transistor comprised of a metal-oxide-semiconductor field-effect transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin transistor comprised of a metal-oxide-semiconductor field-effect transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.

Nonvolatile static random access memory based on spin-transistor architecture

The paper presents functional MOSFET (F-MOSFET) architecture using nonpolar-type resistive switching devices (RSDs) for nonvolatile SRAM (NV-SRAM) application. The architecture can be achieved by connecting a RSD to the source terminal of an ordinary MOSFET. The current drive capability of the F-MOSFET can be modified by the resistance state of the connected RSD, which is a very useful function for recently emerging nonvolatile logic and reconfigurable logic applications. NV-SRAM can be easily configured with a standard SRAM cell and F-MOSFETs. Using our developed SPICE macromodel for nonpolar-type RSDs, the circuit operation of the proposed NV-SRAM cell was computationally simulated.

Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices

We proposed and computationally analyzed a nonvolatile power-gating field-programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits of the NVPG-FPGA. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power gating (PG). The break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET, which allows highly efficient PG operations with fine granularity, were proposed.

http://iopscience.iop.org/article/10.1143/JJAP.51.11PB02/pdf

Nonvolatile Power-Gating Field-Programmable Gate Array Using Nonvolatile Static Random Access Memory and Nonvolatile Flip-Flops Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

Group-IV ferromagnetic semiconductor Ge1−xFex was grown by low-temperature molecular beam epitaxy without precipitation of ferromagnetic Ge–Fe intermetallic compounds. The ferromagnetism of Ge1−xFex films was investigated by magnetic circular dichroism (MCD). In particular, the influence of the Fe content (x=2.0%–17.5%) and growth temperature (100 and 200°C) on the ferromagnetism was carefully studied. The MCD measurements revealed that the overall spectral features reflecting the band structure of the Ge1−xFex films were identical with those in bulk Ge, and that the large spin splitting of the band structure was induced by the incorporation of Fe atoms into the Ge matrix, indicating the existence of s,p‐d exchange interactions. The Ge1−xFex films showed ferromagnetic behavior and the ferromagnetic transition temperature linearly increased with increasing the Fe concentration. These results indicate that the epitaxially grown Ge1−xFex is an intrinsic ferromagnetic semiconductor.

Yusuke Shuto

Papers

Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems

Nonvolatile static random access memory based on spin-transistor architecture

Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices

Nonvolatile Power-Gating Field-Programmable Gate Array Using Nonvolatile Static Random Access Memory and Nonvolatile Flip-Flops Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

Magneto-optical properties of group-IV ferromagnetic semiconductor Ge1−xFex grown by low-temperature molecular beam epitaxy