AbstractThe paper reports design and analysis of the non-uniform body with dual material TFET-based digital inverter. The analysis includes the transient characteristics of the inverter in appearance and non-appearance of interface trap charges. Gaussian distribution of interface trap charge with various concentrations has been taken into account. Further, different delay parameters of the circuit have been calculated, and it is observed that fall time delay of the circuit is less than that of rise time delay. Finally, it is found that the propagation delays of the proposed TFET-based digital inverter are 9.75 ps and 6 ps in occurrence and non-occurrence of interface trap charges, respectively.KeywordsTFETDigital inverterTrap chargesTransient characteristics 

Design and Analysis of Non-uniform Body with Dual Material FET-Based Digital Inverter

Helps readers understand the physics behind MOS devices for low-voltage and low-energy applications • Based on timely published and unpublished work written by expert authors • Discusses various promising MOS devices applicable to low-energy environmental and biomedical uses • Describes the physical effects (quantum, tunneling) of MOS devices • Demonstrates the performance of devices, helping readers to choose right devices applicable to an industrial or consumer environment • Addresses some Ge-based devices and other compound-material-based devices for high-frequency applications and future development of high performance devices. "Seemingly innocuous everyday devices such as smartphones, tablets and services such as on-line gaming or internet keyword searches consume vast amounts of energy. Even when in standby mode, all these devices consume energy. The upcoming 'Internet of Things' (IoT) is expected to deploy 60 billion electronic devices spread out in our homes, cars and cities.

Promising MOS devices for low-voltage and low-energy applications

This paper discusses aspects of gate-to-drain capacitance (Miller capacitance) of lateral tunnel FETs (LTFETs). It is considered how to reduce the mirror capacitance of LTFET.

Yuyang Jiang

Papers

Aspects and Reduction of Miller Capacitance of Lateral Tunnel FETs