Acenes have long been the subject of intense study because of the unique electronic properties associated with their pi-bond topology. Recent reports of impressive semiconductor properties of larger homologues have reinvigorated research in this field, leading to new methods for their synthesis, functionalization, and purification, as well as for fabricating organic electronic components. Studies performed on high-purity acene single crystals revealed their intrinsic electronic properties and provide useful benchmarks for thin film device research. New approaches to add functionality were developed to improve the processability of these materials in solution. These new functionalization strategies have recently allowed the synthesis of acenes larger than pentacene, which have hitherto been largely unavailable and poorly studied, as well as investigation of their associated structure/property relationships.

The larger acenes: versatile organic semiconductors.

Acene werden wegen ihrer einzigartigen elektronischen Eigenschaften, die auf der Topologie ihrer π-Systeme beruhen, seit langem untersucht. Berichte uber die bemerkenswerten Halbleitereigenschaften hoherer Homologe haben in letzter Zeit zu verstarkten Forschungsaktivitaten gefuhrt. Es wurden neue Verfahren zur Synthese, Funktionalisierung und Reinigung sowie zur Herstellung organoelektronischer Bauteile entwickelt. Durch Untersuchungen an hochreinen Acen-Einkristallen wurden die charakteristischen elektronischen Eigenschaften und Kenngrosen fur die Beurteilung von Dunnschichtbauteilen ermittelt. Um die Verarbeitbarkeit in Losung zu verbessern, wurden neuartige Funktionalisierungsmethoden entwickelt. Die fur elektronische Anwendungen erwunschten Eigenschaften nichtfunktionalisierter Acene bleiben bei der Funktionalisierung erhalten. Mit diesen Verfahren wurden kurzlich Derivate hoherer Acene als Pentacen, die zuvor kaum zuganglich waren, erhalten, sodass Struktur-Eigenschafts-Beziehungen untersucht werden konnten.

Höhere Acene: vielseitige organische Halbleiter

To extend the scaling limit of thermal SiO/sub 2/ in the ultrathin regime when the direct tunneling current becomes significant, members of this author's research team at Yale University, in collaboration with the Jet Process Corporation, embarked on a program to explore the potential of silicon nitride as an alternative gate dielectric. In this paper, high-quality silicon nitride (or oxynitride) films made by a novel jet vapor deposition (JVD) technique are described. The JVD process utilizes a high-speed jet of light carrier gas to transport the depositing species onto the substrate to form the desired films. The film composition has been determined to consist primarily of Si and N, with some amounts of O and H. Metal-nitride-Si (MNS) capacitors based on the JVD nitride films deposited directly on Si exhibit relatively low densities of interface traps, fixed charge, and bulk traps. The interface traps at the nitride/Si interface exhibit different properties from those at the SiO/sub 2//Si interface in several aspects. In contrast to the conventional CVD silicon nitride, the high-field I-V characteristics of the JVD silicon nitride fit the Fowler-Nordheim (F-N) tunneling theory over four to five orders of magnitude in current, but do not fit at all the Frenkel-Poole (F-P) transport theory. This is consistent with the much lower concentration of electronic traps in the JVD silicon nitride. Results from the carrier separation experiment indicate that electron current dominates the gate current with very little hole contribution. Both theoretical calculation and experimental data indicate that the gate leakage current in JVD silicon nitride is significantly lower than that in silicon dioxide of the same equivalent oxide thickness. The breakdown characteristics of the JVD nitride are also respectable. Compared to their MOSFET counterparts, MNS transistors exhibit reduced low-field transconductance but enhanced high-field transconductance, perhaps due to the presence of border traps. As expected, the JVD silicon nitride films exhibit very strong resistance to boron penetration and oxidation at high temperatures. These properties, coupled with its room-temperature deposition process, make JVD silicon nitride an attractive candidate to succeed thermal SiO/sub 2/ as an advanced gate dielectric in future generations of ULSI devices.

Making silicon nitride film a viable gate dielectric

Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive interface charges) and acceptor (negative interface charges), present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance the tunneling current of TFET. Various figures of merit such as cutoff frequency $f_{{T}}$ , maximum oscillation frequency $f_{\max}$ , transconductance frequency product, higher order transconductance coefficients $({g}_{{m}1}, {g}_{{m}3})$ , VIP2, VIP3, IIP3, IMD3, zero crossover point, and 1-dB compression point have been investigated, and the results obtained are simultaneously compared with a gate-all-around TFET (GAA-TFET). Simulation results indicate that HD-GAA-TFET is more immune toward the interface trap charges present at the Si/SiO2 interface than the GAA TFET and hence can act as a better candidate for low power switching applications. All simulations have been done on an ATLAS device simulator.

Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability

A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications, such as transconductance gm, transconductance-to-drive current ratio gm/ID, drain resistance RO, intrinsic gain, and unity-gain cutoff frequency fT, are studied for DG n-TFET, with the help of a device simulator, and compared with that for a similar DG n-MOSFET. Although gm is lower, gm/ID is found to be higher in TFET, except for small values of the gate overdrive voltage, indicating that a TFET can produce higher gain at the same power level than a MOSFET. An extremely high RO and, hence, a high intrinsic gain are also observed for a TFET as compared with that for a MOSFET. A complementary TFET amplifier is found to have more than one order of magnitude higher voltage gain than its MOS counterpart. It is also demonstrated that the drain resistance and, hence, the device gain significantly degrade for increasing body thickness of a TFET.

Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

In addition to its attractiveness for ultralow power applications, analog CMOS circuits based on the subthreshold operation of the devices are known to have significantly higher gain as compared to their superthreshold counterpart. The effects of halo [both double-halo (DH) and single-halo or lateral asymmetric channel (LAC)] doping on the subthreshold analog performance of 100-nm CMOS devices are systematically investigated for the first time with extensive process and device simulations. In the subthreshold region, although the halo doping is found to improve the device performance parameters for analog applications (such as gm/Id, output resistance and intrinsic gain) in general, the improvement is significant in the LAC devices. Low angle of tilt of the halo implant is found to give the best improvement in both the LAC and DH devices. Our results show that the CMOS amplifiers made with the halo implanted devices have higher voltage gain over their conventional counterpart, and a more than 100% improvement in the voltage gain is observed when LAC doping is made on both the p- and n-channel devices of the amplifier

Impact of Halo Doping on the Subthreshold Performance of Deep-Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications

Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-m/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal-oxide semiconductor field-effect transistor, particularly for low-power applications It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltages

Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel

Analog circuits based on the subthreshold operation of CMOS devices are very attractive for ultralow power, high gain, and moderate frequency applications. In this paper, the analog performance of 100 nm dual-material gate (DMG) CMOS devices in the subthreshold regime of operation is reported for the first time. The analog performance parameters, namely drain-current (Id), transconductance (gm), transconductance generation factor (gm/Id), early voltage (VA), output resistance (Ro) and intrinsic gain for the DMG n-MOS devices, and and for the DMG p-MOS devices are systematically investigated with the help of extensive device simulations. The effects of different capacitances on the unity-gain frequency are also studied. The DMG CMOS devices are found to have significantly better performance as compared to their single-material gate (SMG) counterpart. More than 70% improvement in the voltage gain is observed for the CMOS amplifiers when dual-material gates, instead of single-material gates, are used in both the n- and p-channel devices.

Abhijit Mallik

Papers

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

Impact of Halo Doping on the Subthreshold Performance of Deep-Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications

Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel

Subthreshold Performance of Dual-Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications