Metal-organic frameworks (MOFs) are typically highlighted for their potential application in gas storage, separations and catalysis. In contrast, the unique prospects these porous and crystalline materials offer for application in electronic devices, although actively developed, are often underexposed. This review highlights the research aimed at the implementation of MOFs as an integral part of solid-state microelectronics. Manufacturing these devices will critically depend on the compatibility of MOFs with existing fabrication protocols and predominant standards. Therefore, it is important to focus in parallel on a fundamental understanding of the distinguishing properties of MOFs and eliminating fabrication-related obstacles for integration. The latter implies a shift from the microcrystalline powder synthesis in chemistry labs, towards film deposition and processing in a cleanroom environment. Both the fundamental and applied aspects of this two-pronged approach are discussed. Critical directions for future research are proposed in an updated high-level roadmap to stimulate the next steps towards MOF-based microelectronics within the community.

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An updated roadmap for the integration of metal–organic frameworks with electronic devices and chemical sensors

This review presents an extensive discussion on the major advances in the field of periodically organized mesoporous thin films (POMTFs) obtained via surfactant templated growth of inorganic or hybrid polymers. A large variety of templating agents can be coupled with inorganic polymerization reactions for the design of periodically organized nanostructured hybrid phases that yield POMTFs. The tuning of the interface between the template and the polymerizing phase and the control over chemical and processing conditions are the key parameters in producing tailor-made POMTFs with a high degree of reproducibility. This dynamic coupling between chemical and processing conditions dictates extensive use of complementary ex situ measurements with in situ characterization techniques that follow, in real time, film formation from the molecular precursor solutions to the final stabilized POMTF. Among modern analytical tools, 2D-GISAXS, ellipsoporosimetry, HRTEM, X-ray reflectometry, WAXS, time-resolved infrared spec...

Design, Synthesis, and Properties of Inorganic and Hybrid Thin Films Having Periodically Organized Nanoporosity†

Probing surface and interface morphology with Grazing Incidence Small Angle X-Ray Scattering

Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Low dielectric constant materials.

It is argued that the behavior of dielectric particles as they shrink in size through micrometric to nanometric scales will be increasingly dominated by the properties of their interfaces with the environment. The various interatomic and intermolecular forces that determine the structure of these interfaces are reviewed with special emphasis on their electrical nature. A number of situations in which passive and dynamic dielectric properties are traceable to nanometric interfacial properties are considered. It is also demonstrated that such interfaces are nanometric electromechanical (NEM) systems which acting collectively also explain piezoelectricity in macroscopic systems. Interfaces are naturally nanometric entities and must have a major role in the future development of nanotechnology. Their ubiquitous employment in living systems is noted and comparison suggests synergistic opportunities.

Interfaces are the dominant feature of dielectrics at the nanometric level

The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the character...

Z. S. Yanovitskaya

Papers

Low dielectric constant materials for microelectronics

Simulations of diffusion barrier deposition on porous low- k films

Barrier deposition on porous low-k films