This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

This paper presents a wireless power transfer system for a motion-free capsule endoscopy inspection. Conventionally, a wireless power transmitter in a specifically designed jacket has to be connected to a strong power source with a long cable. To avoid the power cable and allow patients to walk freely in a room, this paper proposes a two-hop wireless power transfer system. First, power is transferred from a floor to a power relay in the patient's jacket via strong coupling. Next, power is delivered from the power relay to the capsule via loose coupling. Besides making patients much more conformable, the proposed techniques eliminate the sources of reliability issues arisen from the moving cable and connectors. In the capsule, it is critical to enhance the power conversion efficiency. This paper develops a switch-mode rectifier (rectifying efficiency of 93.6%) and a power combination circuit (enhances combining efficiency by 18%). Thanks to the two-hop transfer mechanism and the novel circuit techniques, this system is able to transfer an average power of 24 mW and a peak power of 90 mW from the floor to a 13 mm × 27 mm capsule over a distance of 1 m with the maximum dc-to-dc power efficiency of 3.04%.

A Two-Hop Wireless Power Transfer System With an Efficiency-Enhanced Power Receiver for Motion-Free Capsule Endoscopy Inspection

This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 μm integrated circuits, which have a combined active area of 0.06 mm 2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

Wireless capsule endoscopy (WCE) is a promising technology for direct diagnosis of the entire small bowel to detect lethal diseases, including cancer and obscure gastrointestinal bleeding (OGIB). To improve the quality of diagnosis, some vital specifications of WCE such as image resolution, frame rate and working time need to be improved. Additionally, future multi-functioning robotic capsule endoscopy (RCE) units may utilize advanced features such as active system control over capsule motion, drug delivery systems, semi-surgical tools and biopsy. However, the inclusion of the above advanced features demands additional power that make conventional power source methods impractical. In this regards, wireless power transmission (WPT) system has received attention among researchers to overcome this problem. Systematic reviews on techniques of using WPT for WCE are limited, especially when involving the recent technological advancements. This paper aims to fill that gap by providing a systematic review with emphasis on the aspects related to the amount of transmitted power, the power transmission efficiency, the system stability and patient safety. It is noted that, thus far the development of WPT system for this WCE application is still in initial stage and there is room for improvements, especially involving system efficiency, stability, and the patient safety aspects.

https://www.mdpi.com/1424-8220/14/6/10929/pdf

Application of Wireless Power Transmission Systems in Wireless Capsule Endoscopy: An Overview

A significant requirement of low-cost sensor systems for defect detection and characterization is to bridge the gap of nondestructive testing & evaluation (NDT&E) and structural health monitoring (SHM). This paper introduces an ultra-high frequency (UHF) passive RFID sensor system for crack detection and potential structural monitoring. The working principles and major research challenges are presented for the new concept of NDT&E sensor systems. One novel approach using 3D antenna and kernel principal component analysis (PCA) is investigated and validated in conjunction with two case studies for evaluation of open and closed cracks. This proposed method can partly alleviate the nonlinearity from wireless channel and demonstrate the feasibility of the in-situ motoring through amplitude and phase of tag’s backscattered signals.

Passive RFID sensor systems for crack detection & characterization

The invention discloses vehicle navigation system and method. The system comprises a self parameter acquisition module, a peripheral parameter acquisition module, a search module, a communication module and a computing control module. The occurred crash among vehicles can be forecast in time by searching vehicles meeting search conditions around the vehicle, communicating with the searched surrounding vehicles and transmitting respective driving parameter information and the like with each other, and the driving parameter information is regulated according to a forecast result or the speed and the direction of the vehicle are controlled in time so as to avoid the vehicle crash. The invention also effectively reduces the cost of the vehicle.

Vehicle navigation system and method

Convolutional Neural Network (CNN) has attained high accuracy and it has been widely employed in image recognition tasks. In recent times, deep learning-based modern applications are evolving and it poses a challenge in research and development of hardware implementation. Therefore, hardware optimization for efficient accelerator design of CNN remains a challenging task. A key component of the accelerator design is a processing element (PE) that implements the convolution operation. To reduce the amount of hardware resources and power consumption, this article provides a new processing element design as an alternate solution for hardware implementation. Modified BOOTH encoding (MBE) multiplier and WALLACE tree-based adders are proposed to replace bulky MAC units and typical adder tree respectively. The proposed CNN accelerator design is tested on Zynq-706 FPGA board which achieves a throughput of 87.03 GOP/s for Tiny-YOLO-v2 architecture. The proposed design allows to reduce hardware costs by 24.5% achieving a power efficiency of 61.64 GOP/s/W that outperforms the previous designs.

/pdf/power-efficient-tiny-yolo-cnn-using-reduced-hardware-2hnx9g21t5.pdf

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip communications in a 65-nm CMOS process. The TX implements a quarter-rate multi-multiplexer (MUX)-based four-tap feed-forward equalizer (FFE), where a charge-sharing-effect elimination technique is introduced into the 4:1 MUX to optimize its jitter performance and power efficiency. The RX employs a two-stage continuous-time linear equalizer as the analog front end and integrates a low-cost sign-based zero-forcing engine relying on edge-data correlation to automatically adjust the tap weights of the TX-FFE. By embedding low-pass filters with an adaptively adjusting bandwidth into the data-sampling path and adopting high-linearity compensating phase interpolators, the clock data recovery achieves both high jitter tolerance and low jitter generation. The fabricated TX and RX chipset delivers 40-Gb/s PRBS data at BER 16-dB loss at half-baud frequency, while consuming a total power of 370 mW.

/pdf/a-40-gb-s-quarter-rate-serdes-transmitter-and-receiver-55sytfkjd5.pdf

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

This paper exploits a new charge pump used in integrated solar energy harvesting systems to improve the power efficiency under ultra low supply of under 0.7V supplied by on-chip photodiodes. Compared with conventional charge pumps, improvements of 20% in terms of output voltage gain and conversion efficiency can be achieved by using two symmetrical branches and PMOSFET-only transfer transistors per stage. The proposed circuit is implemented in UMC 0.18µm standard CMOS technology.

Ultra-low-voltage low-power charge pump for solar energy harvesting systems

While wireless endoscopic capsule examining human's large gastrointestinal (GI) cavity, such as stomach and large intestine, it is possible that many interested spots are omitted by the one or two cameras due to its limited field of view. This paper proposes a new globularity capsule endoscopy system with multi-camera. Through analyzing the multi-camera system's optical characteristic and power consumption of the endoscopic capsule system, this paper proposes the spatial physical structure and the electronic architecture of the globularity capsule without blind area. Its diameter can be less than 15mm. The capsule can work in human's GI tract for 8 hours when the image frame rate is 4fps.

Ziqiang Wang

Papers

Vehicle navigation system and method

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

Ultra-low-voltage low-power charge pump for solar energy harvesting systems

A new globularity capsule endoscopy system with multi-camera