An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Nanocomposite photovoltaic devices are provided that generally include semiconductor nanocrystals as at least a portion of a photoactive layer. Photovoltaic devices and other layered devices that comprise core-shell nanostructures and/or two populations of nanostructures, where the nanostructures are not necessarily part of a nanocomposite, are also features of the invention. Varied architectures for such devices are also provided including flexible and rigid architectures, planar and non-planar architectures and the like, as are systems incorporating such devices, and methods and systems for fabricating such devices. Compositions comprising two populations of nanostructures of different materials are also a feature of the invention.

Nanostructure and nanocomposite based compositions and photovoltaic devices

This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Customizable and programmable cell array

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A method for processing a semiconductor wafer, the method including: providing a semiconductor wafer including an image sensor pixels layer including a plurality of image sensor pixels, the layer overlaying a wafer substrate; and then bonding the semiconductor wafer to a carrier wafer; and then cutting off a substantial portion of the wafer substrate, and then processing the substantial portion of the wafer substrate for reuse.

Semiconductor and optoelectronic methods and devices

A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer

A very high speed customizable logic array device comprising: a substrate having at least one gate layer and at least first, second and third metal layers formed thereon, the gate layer including a multiplicity of identical unit logic cells, the customizable logic array device including at least three of the following functionalities: NAND, NOR, inverter, AND and OR and further being characterized in that the ratio between the rise time and the fall time of the logic cells embodying each of the at least three functionalities is constant.

High speed customizable logic array device

An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.

Semiconductor system, device and structure

A device, including: an integrated circuit chip, where the integrated circuit chip includes: a first layer including a plurality of first transistors including a mono-crystal channel; at least one metal layer overlying the first layer, the at least one metal layer including aluminum or copper and providing interconnection between the first transistors; a second layer overlying the at least one metal layer, the second layer including second horizontally oriented transistors including a second mono-crystal channel; and a through the second layer via of diameter less than 150 nm, where the second horizontally oriented transistors are interconnected to form logic circuits.

Zvi Or-Bach

Papers

Semiconductor and optoelectronic methods and devices

Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer

High speed customizable logic array device

Semiconductor system, device and structure

Integrated circuit device and structure