Great Lakes Symposium on VLSI 

About: Great Lakes Symposium on VLSI is an academic conference. The conference publishes majorly in the area(s): CMOS & Very-large-scale integration. Over the lifetime, 2299 publications have been published by the conference receiving 21943 citations.

Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems

Abstract: In microprocessor-based systems, large power savings can be achieved through reduction of the transition activity of the on- and off-chip buses. This is because the total capacitance being switched when a voltage change occurs on a bus line is usually sensibly larger than the capacitive load that must be charged/discharged when internal nodes toggle. In this paper, we propose an encoding scheme which is suitable for reducing the switching activity on the lines of an address bus. The technique relies on the observation that, in a remarkable number of cases, patterns traveling onto address buses are consecutive. Under this condition it may therefore be possible, for the devices located at the receiving end of the bus, to automatically calculate the address to be received at the next clock cycle; consequently, the transmission of the new pattern can be avoided, resulting in an overall switching activity decrease. We present analytical and experimental analyses showing the improved performance of our encoding scheme when compared to both binary and Gray addressing schemes, the latter being widely accepted as the most efficient method for address bus encoding. We also propose power and timing efficient implementations of the encoding and the decoding logic, and we discuss the applicability of the technique to real microprocessor-based designs.

A novel low power energy recovery full adder cell

Abstract: A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low powerful adders; the transmission function adder (TFA) the dual value logic (DVL) adder and the fourteen transistor (14 T) full adder. The proposed SERF adder design was proven to be superior to the other three designs in power dissipation and area, and second in propagation delay only to the DVL adder. The combination of low power and low transistor count makes the new SERF cell a viable option for low power design.

Cooling of integrated circuits using droplet-based microfluidics

Abstract: Decreasing feature sizes and increasing package densities are making thermal issues extremely important in IC design. Uneven thermal maps and hot spots in ICs cause physical stress and performance degradation. Many MEMS and microfluidics-based solutions were proposed in the past. We present a cooling method based on high-speed electrowetting manipulation of discrete sub-microliter droplets under voltage control with volume flow rates in excess of 10 mL/min. We also propose a flow-rate feedback control where the hot areas get increased supply of droplets without the need for external sensors and electrothermocapillary control where hot areas attract droplets due to thermocapillarity and are returned to their reservoirs by electrowetting resulting in a self-contained and a self-regulated system.

Thermal analysis of a 3D die-stacked high-performance microprocessor

Abstract: 3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional planar ICs, 3D ICs have shorter latencies as well as lower power consumption, due to shorter wires. The benefits of 3D ICs increase as we stack more die, due to successive reductions in wire lengths. However, as we stack more die, the power density increases due to increasing proximity of active (heat generating) devices, thus causing the temperatures to increase. Also, the topmost die on the 3D stack are located further from the heat sink and experience a longer heat dissipation path. Prior research has already identified thermal management as a critical issue in 3D technology. In this paper, we evaluate the thermal impact of building high-performance microprocessors in 3D. We estimate the temperatures of a planar IC based on the Alpha 21364 processor as well as 2-die and 4-die 3D implementations of the same. We show that, compared to the planar IC, the 2-die implementation and 4-die implementation increase the maximum temperature by 17 Kelvin and 33 Kelvin, respectively.

Double DIP: Re-Evaluating Security of Logic Encryption Algorithms

Abstract: Logic encryption is a hardware security technique that uses extra key inputs to lock a given combinational circuit. A recent study by Subramanyan et al. shows that all existing logic encryption techniques can be successfully attacked. As a countermeasure, SARLock was proposed to enhance the security of existing logic encryptions. In this paper, we re-evaluate the security of these approaches. A SAT-based attack called Double DIP is proposed and shown to successfully defeat SARLock-enhanced encryptions.