International Conference on Green Circuits and Systems 

About: International Conference on Green Circuits and Systems is an academic conference. The conference publishes majorly in the area(s): Adaptive filter & Digital filter. Over the lifetime, 140 publications have been published by the conference receiving 956 citations.

An enhanced segmentation on vision-based shadow removal for vehicle detection

Abstract: We present an enhanced segmentation method to reduce the interference of shadows for vehicle detection. The main advantage of the proposed method is its low-complexity. We use only the luminance of an image for shadow removal and keep the chrominance components of the image intact. The luminance of the current image is enhanced and each pixel is compared with a pixel-dependent threshold for locating shadow regions. With that, the shadow regions can be located more accurately and the moving objects can be extracted more completely. Experimental results verify the proposed approach and show that it is helpful for vehicle detection.

Image-based vehicle tracking and classification on the highway

Abstract: In recent years, the development of automatic traffic surveillance system has received great attention in the academic and industrial research. Based on computer vision technology, the purpose of this work is to construct the traffic surveillance system on the highway for estimating traffic parameters, such as vehicle counting and classification. The proposed system mainly consists of three steps including vehicle region extraction, vehicle tracking, and classification. The background subtraction method is firstly utilized to extract the foreground regions from the highway scene. Some geometric properties are applied to remove the false regions and shadow removal algorithm is used for obtaining more accurate segmentation results. After vehicle detection, a graph-based vehicle tracking method is used for building the correspondence between vehicles detected at different time instants. Finally, we introduce two measures, such as aspect ratio and compactness to classify vehicles. In the experiment, three videos with different lighting conditions are used to demonstrate the effectiveness of our proposed system.

Construction of constrained multi-bit flip-flops for clock power reduction

Abstract: Based on the elimination feature of redundant inverters in merging 1-bit flip-flops into multi-bit flip-flops, given the congested constraint of unallocated bins and the length constraints of the input and output signals of all the 1-bit flip-flops, an efficient two-phase approach is proposed to obtain the final multi-bit flip-flops. Compared with the original design in the numbers of inverters for two tested examples, the experimental results show that our proposed approach eliminates 68% of inverters to maintain the synchronous designs and saves 19.75% of the clock power on the average for two tested examples in reasonable CPU time.

A green FFT processor with 2.5-GS/s for IEEE 802.15.3c (WPANs)

Abstract: This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the 2.59 Gigasample/s throughput requirements, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced and the proposed radix-16 FFT butterfly processing element (PE) can be optimally pipelined. Specifically, the radix-16 butterfly PE consists of one radix-4 and two radix-2 cascaded pipelined butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to the optimized pipelined structure. Hardware reuse and low-power schemes are also devised to reduce both area and power consumption. Moreover, a multibank memory scheme is used to support up to 16-times I/O capability of a single-bank memory, which can greatly reduce the input/output time of FFT data samples. As a result, the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that the proposed design has 2.59 GS/s throughput and it consumes 103.5 mW by using UMC 90nm process.

A compare-and-write ferroelectric nonvolatile flip-flop for energy-harvesting applications

Abstract: In this paper, a novel compare-and-write ferroelectric nonvolatile flip-flop is developed, which can be used in the checkpoint processor for energy-harvesting applications. It can make the processor nonvolatile, secure and instant recoverable from power failures. The behavior model of ferroelectric capacitor is set up to characterize its electrical property. An improved architecture of ferroelectric capacitor based flip-flop is proposed in which a compare-and-write block is used to decide if the state of ferroelectric capacitor should be changed. Thus, the presented architecture can prolong the lifetime of the ferroelectric capacitor by removing the unnecessary programming cycles. The design is implemented in HJTM 0.18um CMOS process and simulation results show that the proposed ferroelectric nonvolatile flip-flop operates properly and reduces 40–80% programming cycles, which increases the lifetime of the ferroelectric capacitors effectively and expands its application in checkpoint processors for energy-harvesting area.