Conference
Midwest Symposium on Circuits and Systems
About: Midwest Symposium on Circuits and Systems is an academic conference. The conference publishes majorly in the area(s): CMOS & Adaptive filter. Over the lifetime, 6694 publications have been published by the conference receiving 34981 citations.
Topics: CMOS, Adaptive filter, Very-large-scale integration, Artificial neural network, Digital filter
Papers published on a yearly basis
Papers
More filters
09 Aug 1998
TL;DR: The state of the art of SR techniques is reviewed using a taxonomy of existing techniques and areas which promise performance improvements are identified.
Abstract: Growing interest in super-resolution (SR) restoration of video sequences and the closed related problem of construction of SR still images from image sequences has led to the emergence of several competing methodologies. We review the state of the art of SR techniques using a taxonomy of existing techniques. We critique these methods and identified areas which promise performance improvements.
518 citations
12 Aug 1990
TL;DR: In this paper, a variable step size LMS algorithm is proposed, which has a big step size at the beginning for a maximum convergence speed, and a much smaller step size after the convergence, for a minimum residual error.
Abstract: A variable step size LMS algorithm is proposed. The variable step size LMS algorithm has a big step size at the beginning, for a maximum convergence speed, and a much smaller step size after the convergence, for a minimum residual error. The algorithm is derived according to the shortest distance norm between the Kalman gain and the LMS gain vectors. The exponential window is included in the derivation for maintaining a non-zero stable step size. Both the convergence speed and the stable value of the step size can be adjusted. Little additional multiplication is required to implement the algorithm. >
328 citations
04 Aug 2002
TL;DR: In this article, a new scheme for increasing the accuracy of current sensing when the discrete elements are not known is introduced, which measures the inductor value during the DC-DC controller startup.
Abstract: Current sensing is one of the most important functions on a smart power chip. Conventional current-sensing methods insert a resistor in the path of the current to be sensed. This method incurs significant power losses, especially when the current to be sensed is high. Lossless current-sensing methods address this issue by sensing the current without dissipating the power that passive resistors do. Six available lossless current sensing techniques are reviewed. A new scheme for increasing the accuracy of current sensing when the discrete elements are not known is introduced. The new scheme measures the inductor value during the DC-DC controller startup.
319 citations
04 Aug 2002
TL;DR: Simulation results are provided which demonstrate the robustness of the proposed technique to a variety of common image degradations and the results of the approach are compared to other transform domain watermarking methods.
Abstract: In this paper, we present a technique for watermarking of digital images based on the singular value decomposition. Simulation results are provided which demonstrate the robustness of the proposed technique to a variety of common image degradations. The results of our approach are also compared to other transform domain watermarking methods.
173 citations
01 Jan 2002
TL;DR: The simulation and the implementation results show that the fat tree encoder outperforms the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case.
Abstract: The thermometer code-to-binary code encoder has become the bottleneck of ultra-high speed flash ADCs. In this paper, the authors present the fat tree thermometer code-to-binary code encoder that is highly suitable for ultra-high speed flash ADCs. The simulation and the implementation results show that the fat tree encoder outperforms the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder is an effective solution for the bottleneck problem in ultra-high speed ADCs.
120 citations