Showing papers by "Amkor Technology published in 2011"

Next generation fine pitch Cu Pillar technology — Enabling next generation silicon nodes

Abstract: There has been a growing need for fine pitch flip chip technology in support of next generation communication devices with increasing die complexities. The increase in functionality which drives a larger number of signal I/O's in combination with small die size requirements as a result of transistor size reductions have driven the need to investigate finer die interconnect pitches. Traditional solder or Cu Pillar interconnect pitches of 150um to 200um that are currently used in both low and high end flip chip applications are now facing a number of technical limitations as device scaling requirements push the limits of flip chip pad density per square mm of silicon. This paper will review the process development and advancement of several next generation fine pitch Cu Pillar bumping and assembly processes, with pitches less than 60um, that are focused on addressing the challenges seen on silicon nodes such as 65nm and beyond.

Wafer level fan out package

Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

Cu Pillar and μ-bump electromigration reliability and comparison with high pb, SnPb, and SnAg bumps

Abstract: Failures due to Electromigration (EM) in flip-chip bumps have emerged as a major reliability concern due to potential elimination of Pb from flip-chip bumps and a continuous drive to increased IO density resulting in a reduction of bump pitch and size. Additionally, the rapid development and implementation of 3D IC structures introducing new interconnects (μ-bumps, RDL, microvias, and TSVs) at much finer geometries, raises concerns about electromigration and current carrying capacity of these interconnects. This paper presents the results of multiple EM studies on Cu Pillar, High Pb, SnAg, eutectic SnPb Flip Chip bumps and μ-bumps. A special test vehicle was designed to get a head-to-head comparison of Cu Pillar EM with that of solder bumps. Tests are being conducted using three current levels and three temperatures to estimate Black's Equation parameters. A separate test vehicle is also being tested using 5 combinations of current and temperature to estimate the current carrying capacity of Cu-SnAg-Cu μ-bumps of 25um diameter. More than 8000 hours of testing is completed on flip chip solder bump and Cu Pillar, showing Cu Pillars as having the best reliability amongst the four bump metallurgies. The worst reliability was observed for High Pb bumps followed by eutectic SnPb eut and SnAg bumps. The Cu-SnAg-Cu μ-bump structure has been tested for 5500+ hours without any failures. The paper provides the detailed test matrix, failure data, failure analysis, and an estimation of Black's Equation parameters for some of the above configurations on test.

Characterization of intermetallic compound (IMC) growth in Cu wire ball bonding on Al pad metallization

Abstract: As one of the alternative materials in chip interconnection, copper wire has become popular because of its lower cost and higher electrical conductivity than gold wire. Moreover it is known that long term reliability performance at high temperature of copper wire is better than that of gold wire because of slower Cu/Al intermetallic compound (IMC) growth than that of Au/Al intermetallics. However, majority of copper wire bonding development works has been focused on the material and/or process optimization and qualification so far, now it is time that we need to understand more on the Cu/Al IMC growth behavior to prevent IMC related failures in copper wire field application. So, in this paper, we aimed to generate Cu/Al IMC growth model based on the experimental result depends on high temperature storage (HTS) time and temperature and also tried to suggest Cu/Al IMC thickness guideline to minimize IMC degradation. In this experiment, Al pad chips were bonded with 99.99% purity of copper wire and Pd coated copper wire and some of them were encapsulated with epoxy mold compound. The samples were storaged at the temperature range from 150 C to 250 C upto 1000 hrs. IMC phase and thickness were analyzed by the help of SEM and EDX. In order to generate Cu/Al growth model, reaction rate (K) and activation energy (AQ) were calculated with above experimental results by using Arrhenius diffusion equation. Also, in order to investigate the Cu/Al IMC effect on the bondability, ball shear strength was measured and its result was correlated with IMC thickness. According to this paper, we could derive Cu/Al IMC thickness prediction model and suggest IMC thickness guideline that can minimize IMC failures.

A study on an Ultra Thin PoP using through mold via technology

Abstract: This paper presents a study on an Ultra Thin PoP, Package on Package, using Through-Mold-Via Technology (TMV). The total height of the evaluated PoP is approximately 1.0 mm including both top and bottom packages. In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts and reduced thickness. In this study, an existing 0.5mm pitch top package was utilized as a control. An Ultra Thin bottom PoP had to be developed to meet the 1.0mm stack height target which needs advanced thin material and process technologies. The stack height of 1.0mm requires higher warpage control challenge for the bottom package to support different die size applications. This Ultra Thin bottom PoP test vehicle was built in 12mm × 12mm body, 0.5mm top / bottom pitch, 0.15mm thick mold, and die sizes ranging from 5.0mmsq. to 8.7mmsq. This package was tested with 4-layer / 0.23mm thick and 2-layer / 0.17mm thick substrate. The total PoP height is expected to be approximately 1.0mm by SMT one pass reflow stacking of the top memory package on the bottom Ultra Thin logic package. The package warpage was compared for two package configurations. One is bare die structure with assumption of flip chip interconnect. The other is TMV, where the entire package is over molded, and through-mold vias are laser-drilled down to TMV pads for interface with a top memory package. Confirmation has been made that the TMV structure is capable of accommodating larger die compared to bare die structure. This is because CTE in the package can be controlled by both of the substrate and Epoxy Molding Compound (EMC). In addition, the TMV structure has a flatter and more stable warpage profile due to the over molded EMC structure and material properties selected. From the measurement result, warpage amount and direction greatly depend on substrate construction and die size. Based on warpage result, two test vehicle conditions were selected with TMV configuration to carry out Board Level Reliability (BLR) testing. The test vehicle was mounted on board with a typical package stacking process. After on-board reflow process, (i.e. top and bottom PoP packages were reflowed at one time), the yield for package stacking showed good results demonstrated even with the limited set up for this trial. The test vehicle passed Drop Test and TCT (Temperature Cycling Test) criteria.

Crack initiation and growth in WLCSP solder joints

Abstract: Solder fatigue crack initiation and growth was studied in WLCSP assemblies. Samples were surface mounted to test boards, then extracted at regular intervals of thermal cycling. Crack lengths in the corner solder joints were measured using dye-and-pry technique. Four temperature cycle conditions and six solder ball alloys were evaluated. For all alloys and conditions, the cracks initiated near the component pad interface and propagated down into the solder bulk somewhat. Sn0.7Cu had some propensity toward cracks that propagated at approximately 45 degrees from the pad. 63Sn37Pb and Sn0.7Cu had much higher crack growth rates on the outboard side of the joints compared to the inboard side. SAC405, SAC305, SAC125Ni, and Sn3.5Ag had more similar growth rates on outboard and inboard sides of the joints. These differences are believed to be due to the temperature dependence of the creep deformation and damage accumulation in each alloy. 63Sn37Pb, SAC125Ni, and Sn0.7Cu showed a greater number of cycles to crack initiation compared to the other alloys. This trend is likely due to a lower creep resistance, which resulted in reduced tensile stresses at the edge of the solder joints. Sn0.7Cu and SAC405 had the lowest crack growth rates under most of the temperature cycle conditions. The estimated cycles to failure based on the present crack initiation and growth data was compared to previous data from like assemblies that were electrically monitored. It was found that the average crack growth data from individual joints over-estimates the mean fatigue life of components. However, the average + 3 a crack growth data provides a good estimate of first failure fatigue life from components. Statistical arguments are proposed to explain these results.

Top port with interposer MEMS microphone package and method

Abstract: A top port MEMS package includes a substrate and an interposer mounted to the substrate. The interposer includes an interposer aperture and an interposer channel fluidly coupled to the interposer aperture. A MEMS electronic component is mounted to the interposer above the interposer aperture. A top port lid includes a top port and a chimney structure fluidly coupling to the top port to the interposer channel. A front volume including the top port, the flue, the interposer channel, and the interposer aperture is acoustically sealed from a relatively large back volume defined by a lid cavity of the top port lid. By acoustically sealing the front volume from the back volume and further by maximizing the back volume, the noise to signal ratio is minimized thus maximizing the sensitivity of top port MEMS microphone package as well as the range of applications.

Underfill contacting stacking balls package fabrication method and structure

Abstract: Stacking balls are formed on ball terminals prior to application of an underfill under a flip chip mounted electronic component. The underfill is then applied and directly contacts and at least partially encloses an inner row of the stacking balls closest to and directly adjacent the flip chip mounted electronic component. By forming the stacking balls prior to the application of the underfill, contamination of the ball terminals by the underfill is avoided. This allows the spacing between the ball terminals and the electronic component to be minimized.

Molded cavity substrate MEMS package fabrication method and structure

Abstract: A molded ring includes a molded cavity of a molded cavity substrate MEMS package. The molded ring is formed by molding a dielectric material directly upon a substrate. As molding is a relatively simple and low cost process, the molded ring and thus molded cavity are formed at a minimal cost. This, in turn, minimizes the cost of the molded cavity substrate MEMS package.

Advanced laminate carrier module warpage considerations for 32nm pb-free, FC PBGA package design and assembly

Abstract: The trend in large body, high performance integrated circuit packaging for the 32 nm semiconductor node and beyond is towards low dielectric loss to enable high bandwidth / low loss channels, and low thermal expansion to protect fragile, ultra-low dielectric constant (k) chip dielectric materials from differential expansion stress. A low coefficient of thermal expansion (CTE), low dielectric loss laminate composite was developed using industry standard Sequential Build Up (SBU) fabrication techniques and novel laminate materials. This laminate technology was used in assembly of a Flip Chip Plastic Ball Grid Array (FC PBGA) module including a silicon test structure developed for 32 nm Custom Logic development. The same silicon test structure and laminate design were also used to fabricate modules using conventional high volume laminate materials. Various laminate physical parameters including composite CTE were determined. The warpage shape of each laminate was initially characterized at room temperature, and over the temperature range from 25°C to 240°C. Warpage of critical package features was measured and tracked throughout the various steps of the lead free flip chip module assembly process for multiple laminate cross sections, core and buildup materials. A quantity of assemblies of each type was built and measured, data is reported. Advantages and disadvantages of each laminate module type and implications for robust package assembly as evidenced by these results are discussed.

Electronic component package fabrication method and structure

Abstract: A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.

Through via recessed reveal structure and method

Abstract: A stacked assembly includes a stacked structure stacked on a through via recessed reveal structure. The through via recessed reveal structure includes recesses within a backside surface of an electronic component that expose backsides of through vias. Pillars of the stacked structure are attached to the exposed backsides of the through vias through the recesses. The recesses in combination with the pillars work as a lock and key arrangement to insure self-alignment of the pillars with the backsides of the through vias allowing fine pitch interconnections to be realized. Further, by forming the interconnections to the backsides of the through vias within the recesses, the overall thickness of the stacked assembly is minimized. Further still, by forming the interconnections to the backsides of the through vias within the recesses, shorting between adjacent through vias is minimized or eliminated.

Conductive pad on protruding through electrode semiconductor device

Abstract: To form a semiconductor device, a through electrode is formed in a semiconductor die, and a dielectric layer is then formed to cover the through electrode. The dielectric layer has an opening by being partially etched to allow the through electrode to protrude to the outside, or has a thickness thinner overall so as to allow the through electrode to protrude to the outside. Subsequently, a conductive pad is formed on the through electrode protruding to the outside through the dielectric layer by using an electroless plating method.

Advanced coreless flip-chip BGA package with high dielectric constant thin film embedded decoupling capacitor

Abstract: In this paper, coreless flip-chip BGA in Amkor Technology will be introduced with two options First option is a revised coreless substrate design with layer reduction from original core substrate design of flip-chip BGA package and the second one is the coreless substrate with high dielectric constant thin film embedded decoupling capacitor in order to improve power integrity performance The coreless substrate was redesigned to reduce the number of layers for low-cost solution Since the original core substrate has 12 layers (4–4–4) and the revised coreless substrate has 9 layers (8+1), the cost of flip-chip BGA substrate could be reduced Coreless substrates will use ABF films and high dielectric constant thin film to replace core and prepreg dielectric materials and to form embedded decoupling capacitor between power/ground planes

Semiconductor package with patterning layer and method of making same

Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including one or more semiconductor dies which are electrically connected to an underlying substrate through the use of a conductive pattern which is at least partially embedded in a patterning layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate is at least one semiconductor die. The semiconductor die and the substrate are at least partially encapsulated by a patterning layer. Embedded in the patterning layer is a wiring pattern which electrically connects the semiconductor die to the conductive pattern. A portion of the wiring pattern is exposed in the patterning layer.

Stacked and staggered die MEMS package and method

Abstract: A staggered die MEMS package includes a substrate having a converter cavity formed therein. A converter electronic component is mounted within the converter cavity. Further, a MEMS electronic component is mounted to both the substrate and the converter electronic component in a staggered die arrangement. By staggering the MEMS electronic component directly on the converter electronic component instead of locating the MEMS electronic component in a side by side arrangement with the converter electronic component, the total package width of the staggered die MEMS package is minimized. Further, by locating the converter electronic component within the converter cavity and staggering the MEMS electronic component directly on the converter electronic component, the total package height, sometimes called Z-height, of the staggered die MEMS package is minimized.

Semiconductor device capable of preventing dielectric layer from cracking

Abstract: A semiconductor device is disclosed. A conductive pillar for electrically connecting a semiconductor die to a circuit board may be gradually slimmed from the semiconductor die to the circuit board. A dummy conductive layer may be disposed between the semiconductor die and the conductive pillar. A width of an opening for opening a pattern of the circuit board may range from about 50% to 90% of the width of the lower end of the conductive pillar. Accordingly, a mechanical stress is prevented from being transmitted from the conductive pillar to the semiconductor die, or is absorbed by the dummy conductive layer, and thus, preventing cracks of the semiconductor die and a dielectric layer having a low dielectric constant.

Issues in fatigue life prediction model for underfilled flip chip bump

Abstract: Flip Chip (FC) technology has now become mainstream solution for high-performance packages. From commercial gaming machines to high-reliability servers, FC package is gaining more market share over traditional packaging technologies, such as wire bond. Extensive research has been carried out in FC technologies to improve reliability with increasing IO density. In a flip chip package, thermal mismatch between the silicon die, and the substrate causes solder bump failure due to thermal cycling. Typical failures like bump fatigue, package warpage, die low-k or ELK delamination, die backside crack, BGA joint fatigue are still the major challenges in flip chip packages. Appropriate underfill can significantly reduce the risk of bump cracking by reducing stresses on solder bumps. Due to the complex nature of underfilled flip chip package, accurate failure prediction in accelerated or field life condition is very problematic. There are some good predictive models for package warpage, die low K delamination, and BGA fatigue life that have been published in the literature with varying level of accuracy, however, there is no strong predictive model for flip chip bump life prediction with underfill. Very often researchers use BGA fatigue model for flip chip bump life prediction that end up with huge discrepancy with the actual data. Specifically, the interaction between the underfill material and solder bumps is still unknown. Moreover, there is no good modeling methodology for flip chip bump life prediction. Unlike board level reliability testing, most of the package level testing done for flip chip reliability use qualification testing approaches where the test is suspended after a set number of cycles and pass/fail criteria is based on open/short testing after the conclusion of test. This creates difficulty in correlating simulation results with actual life. In this effort, a large die Pb free flip chip test vehicle has been designed to monitor in-situ bumps and BGA joints crack during temperature cycle. Wide range of material variables such as substrate core type, underfill type, package type, and test conditions have been considered in this study. Through this comprehensive package evaluation and simulation studies, both bump and BGA in-situ data for underfilled packages will be collected and to help develop accurate Pb free bump fatigue model for flip chip bumps.

Semiconductor device with increased I/O configuration

Abstract: In accordance with the present invention, there is provided a semiconductor package or device including a uniquely configured leadframe sized and configured to maximize the available number of exposed lands or I/O's in the semiconductor device. More particularly, the semiconductor device of the present invention includes a die pad (or die paddle) defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the lands. At least portions of the die pad, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.

Leadframe for semiconductor package

Abstract: A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

Semiconductor device with micro electromechanical system die

Abstract: In one embodiment, a miniaturized, multi-function, highly integrated and high performance semiconductor device or package includes a microphone implemented using a MEMS (Micro Electro Mechanical System) die. The semiconductor device includes a leadframe and a body collectively defining a port hole. The port hole facilitates the exposure of a diaphragm of the MEMS die in the semiconductor device.

Heat spreader package

Abstract: A heat spreader package includes a substrate having a first surface, first traces on the first surface of the substrate, and an electronic component having an inactive surface mounted to the first surface of the substrate. The electronic component further includes an active surface having bond pads. Bond wires electrically connect the bond pads to the first traces. An inverted pyramid heat spreader includes a first heatsink, a first heatsink adhesive directly connecting the first heatsink to the active surface of the electronic component inward of the bond pads, a second heatsink having an absence of active circuitry, and a second heatsink adhesive directly connecting a first surface of the second heatsink to the first heatsink. The second heatsink adhesive is a dielectric directly between the bond wires and the second heatsink that prevents inadvertent shorting between the bond wires and the second heatsink.

Accurate Theta jc measurement for high power packages

Abstract: Measuring the case temperature is one of the most challenging measurements for determining the junction-to-case thermal resistance (Theta jc) in high power packages. This is especially true for low Theta jc measurement, in which high power is necessary to control accuracy. Inaccurate case temperature measurement would lead to an inaccurate Theta jc value. This study explores different methods for measuring case temperature and quantifies their impact on Theta jc. A new method of cold-plate protruded thermocouple is proposed and compared with commonly adopted method of lid embedded thermistor both experimentally and numerically. It is found correction is not negligible for low Theta jc measurement in both methods due to the temperature difference between the case surface and the thermal probe location. A standard test jig is also proposed to determine the correction for the cold-plate protruded thermocouple experimentally.

Electronic component package fabrication method and structure

Abstract: An electronic component package includes a RDL pattern comprising a redistribution pattern terminal. A buildup dielectric layer is formed on the RDL pattern, the buildup dielectric layer having a redistribution pattern terminal aperture exposing the redistribution pattern terminal. An interconnection ball is formed within the redistribution pattern terminal aperture and on the redistribution pattern terminal. The interconnection ball includes an enclosed portion having an outer concave surface within the buildup dielectric layer. The angle of intersection between the outer concave surface of the interconnection ball and the redistribution pattern is less than 90°. This minimizes stress between the interconnection ball and the redistribution pattern which, in turn, minimizes failure of the bond between the interconnection ball and the redistribution pattern.

Wafer level chip scale package and method of fabricating wafer level chip scale package

Abstract: A wafer level chip scale package includes a first dielectric layer having a first surface, a second surface, and a main through hole passing through the first dielectric layer between the first and second surfaces. A semiconductor die is disposed in the main through hole of the first dielectric layer and including a bond pad disposed away from the first surface of the first dielectric layer. A redistribution layer is electrically connected to the bond pad of the semiconductor die and extends along the second surface of the first dielectric layer. A second dielectric layer covers the first dielectric layer and the redistribution layer and has an opening exposing the redistribution layer. An under bump metal fills the opening of the second dielectric layer and is electrically connected to the redistribution layer. A solder ball is electrically connected to the under bump metal.

Thermal performance of FC M BGA: Exposed molded die compared to lidded package

Abstract: Thermal resistance data were collected using two different style flip chip ball grid array (FCBGA) packages; one with an exposed molded die and a second with a lid. Eleven different heat sink designs and two different thermal interface materials (TIM) were tested to quantify the thermal interaction between heat sink size, base material and TIM resistance as a function of package style. Package style and TIM material did not appreciably change the total thermal resistance (less than 10%) for small heat sinks 50mm × 50mm smaller. The exposed molded die package thermal resistance was 14% smaller than the lidded package when tested with a heat pipe heat sink. An understanding of the long term performance impact of TIM II degradation was investigated using conduction based models. Lidded style packages may increase safety margin when TIM II materials experience pump-out, dry-out or voiding.

Wafer level package fabrication method

Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

Camera module having lens mount with ir filter

Abstract: An image sensor package includes an image sensor, a window, and a molding, where the molding includes a lens holder extension portion extending upwards from the window. The lens holder extension portion includes a female threaded aperture extending from the window such that the window is exposed through the aperture. A lens is supported in a threaded lens support. The threaded lens support is threaded into the aperture of the lens holder extension portion. The lens is readily adjusted relative to the image sensor by rotating the lens support.

Integrated shield package and method

Abstract: An integrated shield electronic component package includes a substrate having an upper surface, a lower surface, and sides extending between the upper surface and the lower surface. An electronic component is mounted to the upper surface of the substrate. An integrated shield is mounted to the upper surface of the substrate and includes a side shielding portion directly adjacent to and covering the sides of the substrate. The integrated shield covers and provides an electromagnetic interference (EMI) shield for the electronic component, the upper surface and sides of substrate. Further, the integrated shield is integrated within the integrated shield electronic package. Thus, separate operations of mounting an electronic component package and then mounting a shield are avoided thus simplifying manufacturing and reducing overall assembly costs.

Interfacial microstructure and mechanical reliability of Cu pillar/Sn-3.5Ag bump for 3D packages

Abstract: Interfacial microstructure and mechanical reliability of Cu pillar/Sn-3.5Ag microbumps during annealing conditions were systematically and quantitatively evaluated. The IMC growth followed a linear relationship with the square root of the annealing time, which means that the IMC growth was controlled by a diffusion mechanism. The shear strength and IMC thickness increased quadratically with annealing time at 150°C, while the amount of solder decreased. It was clearly revealed that there exist strong correlations among IMC growth kinetics, shear strength, and fracture modes in Cu/solder microbumps.