Showing papers by "Amkor Technology published in 2015"

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

Abstract: This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 \microm-diameter, 6 \micro m-height through-silicon vias (TSVs) and 3.4 bsp\microm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

Silicon Wafer Integrated Fan-out Technology

Abstract: The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been drivin...

Multi-die chip on wafer thermo-compression bonding using non-conductive film

Abstract: Advanced chip on wafer (CoW) assembly has emerged as a key assembly technology for enabling advanced silicon nodes and complex integration. Traditional assembly methods for chip attach have proven capable in this approach, but suffer in the area of fillet design rules. Non-conductive films have been in development as a replacement to the liquid pre-applied underfill materials used in fine pitch copper pillar assembly; however implementation has been slowed by unfavorable cost of ownership and low throughput. Results from recent development have proven the feasibility of a multi-die (gang) bond chip on wafer assembly process. Key assembly steps have been validated and major issues have been mitigated through optimization of materials and process parameters. A scale up phase of development has been initiated which targets the bonding of 8 die (4 units) in a chip on wafer format. The results of this scale up will help move the industry toward a process that can deliver advanced assembly design rules at a cost competitive position when compared to incumbent technologies.

Package of finger print sensor and fabricating method thereof

Abstract: Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

Manufacturing method of semiconductor device and semiconductor device thereof

Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.

Semiconductor package with high routing density patch

Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

A feasible method to predict thin package actual warpage based on an FEM model integrated with empirical data

Abstract: One of the current trends for advanced packages is increasingly thinner packaging for mobile devices. Thin packages increase warpage tremendously making control of package warpage very critical and challenging. Furthermore, a thin package is also much more sensitive to various factors including incoming conditions, processing conditions and nonlinear material behaviors. As a result, current warpage models based purely on the finite element method (FEM) have difficulty accurately predicting the warpage of packages in an actual production environment because the models are not able to capture all the complicated process issues as well as material nonlinearities. On the other hand, current advanced packages are mostly custom built with fast development cycles. Avoiding problems requires a feasible method to predict warpage during the package development stage to guide the design improvement. This paper presents a new feasible method to accurately predict package actual warpage in production based on a finite element model integrated with empirical shadow moire warpage data. The unique aspect of this method uses existing empirical warpage data from a broad range of different package types and design parameters to estimate the actual reference temperature point as well as an initial warpage as inputs into the FEM warpage simulation model. The adjusted actual reference temperature and the initial warpage are used to account for any warpage caused by unknown factors in the assembly processes and materials which cannot be captured by the FEM model. Through the product development cycle, the semi-empirical warpage model is continually updated as more and more new empirical data are available making it more and more accurate for next-cycle predictions. This paper uses a Package-On-Package (POP) and a flip-chip Chip-Scale-Package (fcCSP) as test vehicles to illustrate this unique semi-empirical warpage prediction method.

Magnetic shielding package of non-volatile magnetic memory element

Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15 b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall with a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Manufacturing method for semiconductor device

Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness

Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste

Abstract: The need for high performance and multi-functional devices drove silicon manufacturers to introduce ultra-low dielectric constant (ULK) materials into the back-end-of-line (BEOL) of silicon manufacturing. This innovative technology resulted in performance boost and low RC delay as well as reduced power consumption and cross talk. Although ULK provides electrically improved performance compared to previous generation dielectric materials, it brought significant challenge since the ULK dielectric is a porous and brittle material with inferior material properties.

Wafer-level stack chip package and method of manufacturing the same

Abstract: A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.

Embedded trace substrate and method of forming the same

Abstract: In one embodiment, a method for forming an embedded trace substrate includes forming a conductive layer on a carrier A dielectric film is provided on the conductive layer Vias are formed in the dielectric film and extend to portions of the conductive layer A conductive pattern is formed on the dielectric layer and is electrically connected to the conductive layer through the vias The carrier is removed and portions of the conductive layer are selectively removed to provide a plurality of bumps pads configured to protrude outwardly from the dielectric layer

Packaged electronic device having integrated antenna and locking structure

Abstract: A packaged electronic device includes an integrated antenna as part of a conductive leadframe. The conductive leadframe includes a die paddle have an elongated conductive beam structure configured as a transmission line, and a ground plane structure disposed surrounding the die paddle. The ground plane includes a gap where the transmission line extends to an edge of the packaged electronic device. In one embodiment, selected leads within the leadframe are configured with conductive connective structures as ground pins, source pins, and/or wave guides. In an alternate embodiment, a portion of the integrated antenna is embedded and partially exposed within the body of the packaged electronic device.

Method of forming a molded substrate electronic package and structure

Abstract: In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns and a package body encapsulating the top surface of the insulating material and the electronic device, wherein the bottom land surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer.

Semiconductor device with fine pitch redistribution layers

Abstract: A semiconductor device with fine pitch redistribution layers is disclosed and may include a semiconductor die with a bond pad and a first passivation layer comprising an opening above the bond pad. A redistribution layer (RDL) may be formed on the passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region. A second passivation layer may be formed on the RDL with an opening for the connection region of the RDL. An under bump metal (UBM) may be formed on the connection region of the RDL and a portion of the second passivation layer. A bump contact may be formed on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer and may be constant from the bond pad through at least a portion of the opening.

Semiconductor device package and manufacturing method thereof

Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.

Laser assisted bonding for semiconductor die interconnections

Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.

High reliability packaging technologies and process for ultra low k Flip Chip devices

Abstract: Ultra-high density chips are required for higher device performance, lower power consumption and a smaller form factor device. The interconnection between the chip and integrated circuit (IC) reflect these higher densities, smaller feature size can induce electrical interference based on layout and material set. Therefore, when new interlayer dielectric (ILD) materials are introduced into next generation process node, the chip package interaction (CPI) must be fully characterized for process compatibility and reliability.

Transient interface gradient bonding for metal bonds

Abstract: A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu-Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears.

Method of manufacturing a package-on-package type semiconductor package

Abstract: A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof.

2.5D packaging solution — From concept to platform qualification

Abstract: Silicon interposers offer a viable path to perpetuating the trend of increased chip performance per die area, as projected by Moore's law, which can no longer be met by simply shrinking feature sizes. The enablement of such packaging solutions not only requires new processes for Through Silicon Vias (TSV), thin die manufacturing, assembly and test, but also a well-defined concept of process and supply chain. In a joint work between GLOBALFOUNDRIES and Amkor Technology, a test vehicle with focus on processing aspects and chip package interaction (CPI) has been designed, manufactured, tested, and stressed. The findings and data have been used for the definition of a common interposer platform, now available for customers. This paper describes the design and manufacturing concept of the test vehicle, discusses challenges for interposer processing and test, and shares reliability results.

Stacked Semiconductor Package and Manufacturing Method Thereof

Abstract: A stacked semiconductor package and a manufacturing method thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor package in which an upper interposer and/or package are electrically and mechanically coupled to a lower package utilizing an adhesive member comprising conductive particles.

Extending advanced interconnect technology to finer pitches with conventional mass reflow

Abstract: Great efforts have been invested by many equipment and assembly participants to overcome pitch-limited interconnection packaging technology by using advanced solutions like thermo-compression bonding (TB) which enable high placement accuracy and thin-wafer processability. In contrast, the use of conventional convection ovens to achieve high throughput reflow in chip scale packaging has been deemed suitable only for pitches below a certain value, with the exact threshold remaining vague depending on the operator's process and materials of choice. A key factor in this limitation is the choice of bump metallurgy used, thus solder bumps seems to reach a limit around 150-140-µm pitch vs. copper pillar, whose critical geometry is more definable during plating process, seems to be limited for mass reflow (MR) applications to a pitch around 100 µm.

Semiconductor device having single layer substrate and method

Abstract: In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

Semiconductor package structure for improving die warpage and manufacturing method thereof

Abstract: A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.

Copper foil exposed structure for thin PoP warpage improvement

Abstract: Advanced flip chip packaging technology supports the next generation of products with increased die complexities. The increase in complexity and functionality has been driving the need to investigate fine-pitch interconnection technology with 3D integration. Recently, Package on Package (PoP) has emerged as the preferred 3D integration of logic processors and memory devices for mobile handsets and portable applications. The current PoP solution consists of memory die in the top package stacked on logic function die in the bottom package. Various challenges also need to be met to support the volume production and establish reliable manufacturing process for PoP platform.

Semiconductor chip testing apparatus

Abstract: A semiconductor chip testing apparatus is disclosed. The semiconductor chip testing apparatus includes: an upper socket unit which is formed therein with a receiving space receiving an upper semiconductor chip, holds a lower semiconductor chip using a suction airflow passing around the upper semiconductor chip in the receiving space, and electrically connects the lower semiconductor chip to the upper semiconductor chip; a blade block coupled to the upper socket unit to deliver a vacuum pressure for generating the suction airflow in the receiving space; and a lower socket unit on which the lower semiconductor chip held by the upper socket unit is seated, and which is electrically connected to the seated lower semiconductor chip.

Semiconductor package with semiconductor die directly attached to lead frame and method

Abstract: In one embodiment, a semiconductor package includes a semiconductor die having conductive pads. A lead frame is directly connected to the conductive pads using an electrochemically formed layer or a conductive adhesive layer thereby facilitating an electrical connection between the conductive pads of the semiconductor die and the lead frame without using separate wire bonds or conductive bumps.

Localized TIM characterization using deconstructive analysis

Abstract: Characterizing the thermal performance of thermal interface materials (TIMs) continues to be a challenge for flip chip ball grid array (FCBGA) packages. Steady-state methods have been studied extensively but due to the difficulty in making accurate case temperature measurements have accuracy limitations. Transient measurement techniques offer an attractive alternative to steady state. However, the implementation of a property extraction analysis is more difficult to perform for thermal die with discrete heater cells as found in this study. An experimentally based deconstruction method is presented to predict the local thermal resistance of TIMs as a function time and position on the die over a short pulse ranging from 0.7ms to 100ms. The model is developed for a particular TIM but can be extended to other TIMs following the proposed calibration procedure.