Showing papers by "Cadence Design Systems published in 1992"

Electronic CAD Frameworks

Abstract: The CAD framework, i.e. the underlying facilities provided to the CAD tool developer, the CAD system integrator, and the end-user (IC or system designer) to facilitate their tasks, is discussed. The development of the CAD framework concept in the domain of electronic circuit design is reviewed. The most important work in the area is briefly described. The major components of a CAD framework are identified, and the requirements and desirable features of these components are described in some detail. Many of the key engineering tradeoffs required to build CAD frameworks are examined, using examples from existing CAD systems. Framework standardization efforts are also reviewed. >

A physical model for MOSFET output resistance

Abstract: The output resistance (R/sub out/) most important device parameters for analog applications. However, it has been difficult to model R/sub out/ correctly. In this paper, we present a physical and accurate output resistance model that can be applied to both long-channel and submicrometer MOSFETs. Major short channel effects and hot-carrier effect, such as channel-length modulation (CLM), drain-induced-barrier-lowering (DIBL) and substrate current induced output resistance reduction, are all included in this model, and it is scalable with respect to different channel length L, gate oxide thickness T/sub ox/ and power supply V/sub dd/. This model can be incorporated into existing MOSFET's model without introducing discontinuity. >

Multiple-layer contour searching method and apparatus for circuit building block placement

Abstract: Apparatus and methods for two-dimensional compaction of object collections defines an initial set of unrefined objects and an initial compaction direction. One by one, each unrefined object is taken from the unrefined object configuration and placed within a refined configuration. Both unrefined and refined configurations possess profiles along which the selected object is placed. Pruning rules select which locations to investigate more closely, by eliminating those positions that clearly do not provide compaction improvement. Various orientations and/or shapes of an object can be tried to improve the compaction or the group of objects. Once a best location for the object is found, the object is included in the refined object set, new unrefined and refined profiles are constructed, and a new unrefined object is selected to place. Once all unrefined objects have been selected and placed, the compaction process for the chosen direction has completed. The process can continue for other compaction directions, and as many times as required, to compact the collection of objects within a certain tolerance. The cost function employed to determine best object positions can include costs of wire interconnection lengths.

Hierarchical ordering of logical elements in the canonical mapping of net lists

Abstract: A system and method are described for decreasing the synthesis time required for realizing digital circuit net lists using library logic elements. The system consists of a logic processor working in concert with a cell library register, a hierarchical cell array memory, and a match register, for the purpose of hierarchically ordering, matching and eliminating equivalencies in the canonical forms of library cells. The method includes the reduction of all library elements to their canonical forms and the hierarchical ordering of the these canonicals based on the number of nodes contained in each element. Once ordered, the canonicals are mapped by logic elements having fewer nodes, beginning with the simplest of the canonical forms. Redundantly mapped logical elements are eliminated and the resulting reduced set is stored for subsequent use.

Method and apparatus for optimizing computer file compilation

Abstract: A system and a method are described for optimizing the sequencing and time requirements for compiling large sets of source code residing in multiple hierarchical file directories using an abstracted logical description of the hierarchical file relations existing between directories. The system consists of a logic processor working in concert with input and output file registers, a match register, and an abstracted tree register for the purpose of creating a identifying, comparing, and sequencing file names in a final description of the global directory. The method iteratively identifies the primary input files and the intermediate input files for a given output file for each of a series of directories, inverts the casual relationship between the output file and its intermediary input files, and accumulates and stores these relationships in a sequential manner for subsequent use.

Hier archical pitchmaking compaction method and system for integrated circuit design

Abstract: A hierarchical pitchmatching compactor is provided that maintains hierarchical structure, design rule correctness, and circuit integrity of a symbolic layout while globally compacting the layout without excessive computational or data handling requirements, even for layouts of substantial size. The compactor achieves this result by taking advantage of the regularity of the layout, to reduce the number of constraints in the linear programming problem to a minimum level. This minimal problem, called the minimum design, can be drastically smaller than the original minimization problem for layouts of practical interest. This technique is implemented by means of a computer program that operates on the original symbolic layout of an integrated circuit to produce an automatically compacted layout as the data output.

Cloning method and system for hierarchical compaction

Abstract: A computer system and computer-implemented method for compacting the geometrical area of a hierarchical integrated circuit layout. The present invention is particularly adapted for use with layouts including over-the-cell routing (OTCR). The inventive method includes the general steps of normalizing the cells, compacting the cells, then reconstructing the layout that includes the normalized cells. More particularly, the step of normalizing the cells includes initial step of identifying an overlapping object produced from the OTCR that overlaps one of the instances. That overlapping object is then divided into an overlapping segment and a non-overlapping segment. The overlapping segment is then removed from the cell and copied into the leaf cell of the overlapped instance. The overlapping segment is defined as a special object of the cell into which it is copied.

Device for charging combustible solids to rotary kilns

Abstract: An apparatus (28) is provided for charging combustible solids (30) through a port (35) in the wall (37) of a rotating kiln (10) into a heated zone of the kiln. The apparatus (28) includes a port closure (36) comprising inner and outer portions (64, 62) which cooperate to define a passage (86) for closure-cooling air flow when the closure (36) is in a port-closed position. A transfer assembly (34) is mounted on the kiln wall (37) in aligment with the port (35). During kiln rotation combustible solids (30) are loaded from a staging assembly (32) onto the transfer assembly (34) for aligment with the port (35) and delivery into the kiln (10).

Portable agitator for fluidizing bottom solids in tanks

Abstract: A portable agitator is provided for fluidizing contents of a tank car that has settled during shipment. The agitator includes a column that can extend into a tank car through a manway, a wedging assembly for holding the column in place in the tank between the manway and the bottom wall of the tank, and a pivotable impeller platform appended to a distal end of the column. A pair of impellers are mounted on opposite ends of the impeller platform and are operable to stir and fluidize the contents of the tank car.

On properties of algebraic transformations and the synthesis of multifault-irredundant circuits

Abstract: The authors explore the relationship between algebraic transformations for area optimization and the testability of combinational logic circuits. It is shown that for each multifault in an algebraically factored circuit there is an equivalent multifault in the original circuit. Using this result, it is shown how algebraic factorization may be applied to minimized two-level circuits, to synthesize area-optimized, completely multifault testable multilevel circuits. When a circuit is synthesized using algebraic factorization from a minimized two-level circuit, a reasonably small set of tests that give complete multifault coverage of the synthesized circuit can be derived from the single-fault tests for the original two-level circuit. It is shown that single-fault testability is not an invariant maintained by algebraic transformations, and a simple single-fault irredundant circuit on which the application of algebraic transformations activate a latent multifault, making the resulting algebraically transformed circuit single-fault redundant is presented. >

Method and means for communication between simulation engine and component models in a circuit simulator

Abstract: An apparatus and method for improved efficiency of operation of a circuit simulator. The simulation engine processor sends signals via flag registers to the component model processors to indicate which type of response is required from each component model. The component model processors send back only the requested response, thus minimizing processing time by avoiding generating response types that are not needed. Flexibility is enhanced by centralizing tasks in the simulation engine rather than in the component models, in order to facilitate experimentation and variation in circuit configurations without extensive modifications of component model design.

Waste fuel delivery to long kilns

Abstract: A method is described for environmentally sound usage of combustible hazardous waste in an operating rotary kiln. The method is particularly adapted for disposal of solid hazardous wastes, optionally in the form of a blended waste homogenate, Packaged in sealable containers. The containers are used as fuel modules and charged into a rotary kiln cylinder where kiln gas temperatures range from about 950° to about 1200° C. to achieve high destruction and removal efficiencies.

Hierarchical pitchmatching compaction using minimum design

Abstract: A new hierarchical compactor capable of compacting and pitchmatching hierarchically defined layouts is described. The hierarchical compactor can handle most input hierarchies, including multilevel hierarchies, over the cell routing and cell rotations and reflections. The compactor simultaneously compacts the contents of all the cells of the layout hierarchy maintaining the hierarchy of the input layout as well as the pitchmaking and abutment constraints between the cells. The hierarchical compactor automatically factors out the regularity in the layout and performs almost all of its operations on a minimum design. This novel and unique formulation of the hierarchical compaction problem enables compaction time to be a function of the irregularity rather than the size of the layout. >

Apparatus and method for charging combustible solids into a rotary kiln

Abstract: A firing system is provided for charging a plurality of incoming combustible fuel modules containing a known amount of a parameter of interest into a heated zone of a rotating kiln. The firing system separates incoming fuel modules into a plurality of stages based on the parameter amount in each fuel module. The system then removes fuel modules from the plurality of stages in a selected order to maintain an average parameter amount for fuel modules charged into the kiln at substantially a preselected level. The system charges fuel modules into the kiln in the selected order. The system determines an optimum time to charge each fuel module into the rotating kiln to maintain an average amount of the parameter of interest supplied to the kiln substantially at the preselected level.

The CAD Framework Initiative

Abstract: No description of CAD Frameworks would be complete without a discussion of the standardization work being promoted by the CAD Framework Initiative (CFI). This grassroots organization has not only demonstrated beyond doubt the deep belief in standards which is shared by CAD users and vendors in both the Systems and IC markets, but it also has demonstrated remarkable progress in the first three years of its life: both in the production of standards specifications, and in the creation of live demonstrations of interoperability between frameworks and tools at the Design Automation Conferences of 1990 and 1991. Increasingly strong financial support augers well for the continued success of CFI.

An improved power MOSFET macro model for SPICE simulation

Abstract: The SPICE MOSFET model was originally designed for modeling small signal lateral MOSFETs. Due to structural differences between small signal IC FETs and large geometry vertical FETs, the model is not able to simulate a power MOSFET accurately. Several macro models have been developed to overcome this problem. These models have served power designers well. However, inaccuracies in the gate charge and switching time characteristics cannot satisfy the needs of designers in the simulation of modern high frequency power supply design. To improve the accuracy of gate charge and switching time characteristics, a new model is developed based on the approach proposed by C.E. Cordonnier. In the new model an arbitrary current source is used to model the nonlinear gate to drain capacitance, Cgd. To improve simulation efficiency, the model avoids the use of any switches, which often cause voltage discontinuities. The model is fully tested in a variety of test circuits and results are compared to data sheet information to demonstrate the accuracy of this new model.< >

Cloning techniques for hierarchical compaction

Abstract: True hierarchical compaction maintains input layout hierarchy as well as abutment constraints between cells. The bottleneck for hierarchical compaction is the time taken to analyze the system of equations which must be solved via linear programming methods. Because of the computational complexity of linear programmin it is essential to keep this system of equations as smal?as possible. With over the cell routing the amount of interaction between levels of hierarch increases considerably. This causes a substantial rise in tXe number of constraints and so the time taken by the compaction rocess is significantly increased. A novel method for hanAing over the cell routing, termed cloning, is described. This approach allows for efficient compaction of arbitrary hierarchies containing ouer the cell routing without significantly degrading the run time performance of the hierarchical compactor. 1 Overview 1.1 Background

Cloning techniques for hierarchical compaction

Abstract: A method for efficiently performing hierarchical compaction in the presence of over the cell routing (OTCR) is described. By treating the OTCR objects as part of the cells they overlap, the amount of interaction between cells in the hierarchy is reduced. This method eliminates the need to make all objects within a cell that interact with OTCR into ports. An explosion in the complexity of the problem that needs to be solved via linear programming (LP) is thus avoided. Computation is shifted away from LP and into the graph domain where efficient and accurate solution methods have been demonstrated. >

Design Flow Management

Abstract: The notion underlying Design Flow Management (DFM), or Design Methodology Management, is that chip design is a process, involving a sequence of operations, performed on design data. DFM software attempts to capture and automate that process.

Routing considerations in symbolic layout synthesis

Abstract: The authors discuss routing styles, including a newly proposed hybrid routing style, in basic silicon-level design for a symbolic layout synthesis tool with practical considerations for design rules and process technology. Methods for systematically adding jogs in the layout to achieve high layout quality are proposed. Algorithms for input/output-pin assignment and for pin-ordering routing that achieve a minimal number of vias are also presented. Experiments on real industry designs showed promising results. >

Analogue and mixed-signal IC design

Abstract: Implementing analogue functions on ICs is getting easier, creating a booming market for analogue ASICs

A circuit component placer for optimizing layout with arbitrarily shaped rectilinear and soft blocks

Abstract: A novel circuit component placement algorithm to place arbitrarily shaped rectilinear and soft blocks is proposed. Experimental results on randomly generated cases and industrial examples demonstrate that the algorithm can both find a very compact placement and minimize the wire length. >